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C8051F969 데이터시트 PDF




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부품번호 C8051F969 기능
기능 Ultra Low Power 128K LCD MCU
제조업체 Silicon Laboratories
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C8051F969 데이터시트, 핀배열, 회로
C8051F96x
Ultra Low Power 128K, LCD MCU Family
Ultra Low Power Consumption at 3.6 V
- 130 µA/MHz Low-Power Active mode with dc-dc
enabled
- 120 nA sleep current w/ data retention; POR monitor
enabled
- 450 nA sleep mode with SmaRTClock
(internal LFO)
- 600 nA sleep mode with SmaRTClock (ext. crystal)
- 2 µs wakeup time; 1.5 µA analog settling time
12-Bit; 16 Ch. Analog-to-Digital Converter
- Up to 75 ksps (12-bit mode) or 300 ksps
(10-bit mode)
- External pin or internal VREF (no ext cap required)
- On-chip voltage reference; 0.5x gain allows measur-
ing voltages up to twice the reference voltage
- Autonomous burst mode with 16-bit auto-averaging
accumulator
- Integrated temperature sensor
Two Low Current Comparators
- Programmable hysteresis and response time
- Configurable as wake-up or reset source
Internal 6-Bit Current Reference
- Up to ±500 µA; source and sink capability
- Enhanced resolution via PWM interpolation
Integrated LCD Controller
- Supports up to 128 segments (32x4)
- LCD controller consumes only 400 nA for
32-segment static display
- Integrated charge pump for contrast control
Metering-Specific Peripherals
- DC-DC buck converter allows dynamic voltage
scaling for maximum efficiency (250 mW output)
- Sleep-mode pulse accumulator with programmable
switch, de-bounce and pull-up control; interfaces
directly to metering sensor
- Data Packet Processing Engine (DPPE) includes
hardware AES, DMA, CRC and encoding blocks for
acceleration of wireless protocols
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
Memory
- Up to 128 kB Flash; In-system programmable; Full
read/write/erase functionality over supply range
- Up to 8 kB internal data RAM
Digital Peripherals
- 57 or 34 port I/O; All 5 V tolerant with high sink
current and programmable drive strength
- Hardware SMBus™ (I2C™ Compatible), 2 x SPI™,
and UART serial ports available concurrently
- Four general purpose 16-bit counter/timers
- Programmable 16-bit counter/timer array with six
capture/compare modules and watchdog timer
Clock Sources
- Precision Internal oscillator: 24.5 MHz, 2% accuracy
supports UART operation; spread-spectrum mode
for reduced EMI
- Low power internal oscillator: 20 MHz
- External oscillator: Crystal, RC, C, or CMOS Clock
- SmaRTClock oscillator: 32 kHz Crystal or 16.4 kHz
internal LFO
On-Chip Debug
- On-chip debug circuitry facilitates full-speed, non-
intrusive in-system debug (no emulator required)
- Provides 4 breakpoints, single stepping
Packages
- 76-pin DQFN (6 x 6 mm)
- 40-pin QFN (6 x 6 mm)
- 80-pin TQFP (12 x 12 mm)
Temperature Range: –40 to +85 °C
C2CK/RST
VBAT
VDC
VBATDC
IND
GNDDC
CAP
GND
Power On
Reset/PMU
Wake
Reset
Debug /
Programming
Hardware
CIP-51 8051
Controller Core
128k Byte ISP Flash
Program Memory
256 Byte SRAM
8092 Byte XRAM
C2D
VBAT
VDD
VREG
Analog
Power
Digital
Power
DC/DC Buck
Converter
Precision
24.5 MHz
Oscillator
DMA
CRC
Engine
AES
Engine
Encoder
SYSCLK
LCD Charge
Pump
Low Power
20 MHz
Oscillator
XTAL1
XTAL2
External
Oscillator
Circuit
XTAL3
XTAL4
Enhanced
smaRTClock
Oscillator
System Clock
Configuration
SFR
Bus
Port I/O Configuration
Digital Peripherals
UART
Timers
0, 1, 2, 3
PCA/WDT
SMBus
Priority
Crossbar
Decoder
SPI 0
SPI 1
(DMA Enabled)
Crossbar Control
LCD (up to 4x32)
EMIF
Pulse Counter
Analog Peripherals
Internal External
VREF VREF
12-bit
75ksps
ADC
A
M
U
X
VDD
VREF
Temp
Sensor
GND
CP0, CP0A +
-
CP1, CP1A +
-
Comparators
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
P3-6
Drivers
P7
Driver
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
P1.0/PC0
P1.1/PC1
P1.2/XTAL3
P1.3/XTAL4
P1.4
P1.5/INT5
P1.6/INT6
P1.7
P2.0/SCK1
P2.1/MISO1
P2.2/MOSI1
P2.3/NSS1
P2.4
P2.5
P2.6
P2.7
32
P3.0...P6.7
16
P7.0/C2D
Rev. 1.0 7/13
Copyright © 2013 by Silicon Laboratories
C8051F96x




C8051F969 pdf, 반도체, 판매, 대치품
C8051F96x
5.10. External Voltage Reference........................................................................... 101
5.11. Internal Voltage Reference............................................................................ 101
5.12. Analog Ground Reference............................................................................. 101
5.13. Temperature Sensor Enable ......................................................................... 101
5.14. Voltage Reference Electrical Specifications .................................................. 102
6. Programmable Current Reference (IREF0).......................................................... 103
6.1. PWM Enhanced Mode..................................................................................... 103
6.2. IREF0 Specifications ....................................................................................... 104
7. Comparators........................................................................................................... 105
7.1. Comparator Inputs........................................................................................... 105
7.2. Comparator Outputs ........................................................................................ 106
7.3. Comparator Response Time ........................................................................... 107
7.4. Comparator Hysterisis ..................................................................................... 107
7.5. Comparator Register Descriptions .................................................................. 108
7.6. Comparator0 and Comparator1 Analog Multiplexers ...................................... 112
8. CIP-51 Microcontroller........................................................................................... 115
8.1. Instruction Set.................................................................................................. 116
8.1.1. Instruction and CPU Timing .................................................................... 116
8.2. CIP-51 Register Descriptions .......................................................................... 121
9. Memory Organization ............................................................................................ 124
9.1. Program Memory............................................................................................. 124
9.1.1. MOVX Instruction and Program Memory ................................................ 127
9.2. Data Memory ................................................................................................... 127
9.2.1. Internal RAM ........................................................................................... 127
9.2.2. External RAM .......................................................................................... 128
10. External Data Memory Interface and On-Chip XRAM ....................................... 129
10.1. Accessing XRAM........................................................................................... 129
10.1.1. 16-Bit MOVX Example .......................................................................... 129
10.1.2. 8-Bit MOVX Example ............................................................................ 129
10.2. Configuring the External Memory Interface ................................................... 130
10.3. Port Configuration.......................................................................................... 130
10.4. Multiplexed and Non-multiplexed Selection................................................... 134
10.4.1. Multiplexed Configuration...................................................................... 134
10.4.2. Non-multiplexed Configuration.............................................................. 134
10.5. Memory Mode Selection................................................................................ 135
10.5.1. Internal XRAM Only .............................................................................. 136
10.5.2. Split Mode without Bank Select............................................................. 136
10.5.3. Split Mode with Bank Select.................................................................. 136
10.5.4. External Only......................................................................................... 136
10.6. Timing .......................................................................................................... 137
10.6.1. Non-Multiplexed Mode .......................................................................... 139
10.6.2. Multiplexed Mode .................................................................................. 142
11. Direct Memory Access (DMA0)........................................................................... 146
11.1. DMA0 Architecture ........................................................................................ 147
11.2. DMA0 Arbitration ........................................................................................... 148
3 Rev. 1.0

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C8051F969 전자부품, 판매, 대치품
C8051F96x
20.5. Selecting the Optimum Switch Size............................................................... 271
20.6. DC-DC Converter Clocking Options .......................................................... 271
20.7. Bypass Mode................................................................................................. 272
20.8. DC-DC Converter Register Descriptions ....................................................... 272
20.9. DC-DC Converter Specifications ................................................................... 276
21. Voltage Regulator (VREG0)................................................................................. 277
21.1. Voltage Regulator Electrical Specifications ................................................... 277
22. Reset Sources ...................................................................................................... 278
22.1. Power-On Reset ............................................................................................ 279
22.2. Power-Fail Reset ........................................................................................... 280
22.3. External Reset ............................................................................................... 283
22.4. Missing Clock Detector Reset ....................................................................... 283
22.5. Comparator0 Reset ....................................................................................... 283
22.6. PCA Watchdog Timer Reset ......................................................................... 283
22.7. Flash Error Reset .......................................................................................... 284
22.8. SmaRTClock (Real Time Clock) Reset ......................................................... 284
22.9. Software Reset .............................................................................................. 284
23. Clocking Sources................................................................................................. 286
23.1. Programmable Precision Internal Oscillator .................................................. 287
23.2. Low Power Internal Oscillator........................................................................ 287
23.3. External Oscillator Drive Circuit..................................................................... 287
23.3.1. External Crystal Mode........................................................................... 287
23.3.2. External RC Mode................................................................................. 289
23.3.3. External Capacitor Mode....................................................................... 290
23.3.4. External CMOS Clock Mode ................................................................. 290
23.4. Special Function Registers for Selecting and Configuring the
System Clock ................................................................................................ 291
24. SmaRTClock (Real Time Clock).......................................................................... 295
24.1. SmaRTClock Interface .................................................................................. 296
24.1.1. SmaRTClock Lock and Key Functions.................................................. 297
24.1.2. Using RTC0ADR and RTC0DAT to Access SmaRTClock
Internal Registers.................................................................................. 297
24.1.3. SmaRTClock Interface Autoread Feature ............................................. 297
24.1.4. RTC0ADR Autoincrement Feature........................................................ 297
24.2. SmaRTClock Clocking Sources .................................................................... 300
24.2.1. Using the SmaRTClock Oscillator with a Crystal or
External CMOS Clock ........................................................................... 300
24.2.2. Using the SmaRTClock Oscillator in Self-Oscillate Mode..................... 301
24.2.3. Using the Low Frequency Oscillator (LFO) ........................................... 301
24.2.4. Programmable Load Capacitance......................................................... 301
24.2.5. Automatic Gain Control (Crystal Mode Only) and SmaRTClock
Bias Doubling ........................................................................................ 302
24.2.6. Missing SmaRTClock Detector ............................................................. 304
24.2.7. SmaRTClock Oscillator Crystal Valid Detector ..................................... 304
24.3. SmaRTClock Timer and Alarm Function ....................................................... 304
Rev. 1.0
6

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