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LC0821-SFDWH6-D 데이터시트 PDF




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LC0821-SFDWH6-D 데이터시트, 핀배열, 회로
LCD Module Specification
Model No.: LC0821-BMDWH6-D
LC0821-SFDWH6-D
Table of Contents
1. BASIC SPECIFICATIONS ····························································· 2
2. ABSOLUTE MAXIMUM RATINGS ················································ 3
3. ELECTRICAL CHARACTERISTICS ············································· 4
4. OPERATING PRINCIPLES & METHODS ···································· 7
5. MPU INTERFACE ········································································ 12
6. DISPLAY CONTROL INSTRUCTIONS ······································ 16
7. ELECTRO-OPTICAL CHARACTERISTICS ······························· 21
8. DIMENSIONAL OUTLINE ·························································· 22
9. LCD MODULE NUMBERING SYSTEM ····································· 23
10. PRECAUTIONS FOR USE OF LCD MODULE ·························· 24
RECORD OF REVISION
Rev.
Date
Page
0.1 2007/11/12
-
Item
-
New release
Description




LC0821-SFDWH6-D pdf, 반도체, 판매, 대치품
LC0821-xxDWH6-D Rev 0.1
-4-
3. ELECTRICAL CHARACTERISTICS
3.1 DC Characteristics (Ta=25°C)
Item
Supply Voltage
(Logic)
Supply Voltage
(LCD Drive)
Symbol
VDD
VDD-VO
Condition
Min.
2.7
-
Input High Voltage
VDD=4.5 to 5.5V 2.5
VIH
VDD=2.7 to 4.5V 0.7VDD
Input Low Voltage
Output High Voltage
Output Low Voltage
Supply Current
(Logic)
VIL
VOH
VOL
IDD
VDD=4.5 to 5.5V -0.3
VDD=2.7 to 4.5V
VDD=4.5 to 5.5V
IOH=-0.1mA
VDD=2.7 to 4.5V
IOH=-0.1mA
VDD=4.5 to 5.5V
IOH=0.1mA
VDD=2.7 to 4.5V
IOH=0.1mA
-0.3
2.4
0.75VDD
0
0
VDD=5.0V
-
Typ.
-
5.0
-
-
-
-
-
-
-
-
1.2
Max. Unit
5.5 V
-V
VDD
VDD
0.6
0.55
VDD
V
V
V
V
V
VDD
V
0.4 V
0.2VDD V
3.0 mA
3.2 Interface Timing Chart (Ta=25°C)
Mode
Write Mode
(Refer to
MPU Write
Timing)
Read Mode
(Refer to
MPU Read
Timing)
Characteristic
E Cycle Time
E Rise/Fall Time
E Pulse Width (High,Low)
R/W and RS Setup Time
R/W and RS Hold Time
Data Setup Time
Data Hold Time
E Cycle Time
E Rise/Fall Time
E Pulse Width (High,Low)
R/W and RS Setup Time
R/W and RS Hold Time
Data Output Delay Time
Data Hold Time
VDD=4.5 to 5.5V VDD=2.7 to 4.5V
Symbol
Min. Max. Min. Max.
tC 400 - 1000 -
tR, tF
-
25
-
25
tW 150 - 450 -
tSU1 30 - 60 -
tH1 10 - 20 -
tSU2 40
- 195 -
tH2 10 - 10 -
tC 400 - 1000 -
tR, tF
-
25
-
25
tW 150 - 450 -
tSU 30 - 60 -
tH 10 - 20 -
tD - 100 - 360
tDH 5 - 5 -
Unit
ns
ns

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LC0821-SFDWH6-D 전자부품, 판매, 대치품
LC0821-xxDWH6-D Rev 0.1
-7-
4. OPERATING PRINCIPLES & METHODS
4.1 Register
The LCD controller has two 8-bit registers, the Instruction register (IR) and the data register
(DR).
The IR is a write only register to store instruction codes like Display Clear or Cursor Shift
as well as addresses for the Display Data RAM (DDRAM) or the Character Generator RAM
(CGRAM).
The DR is a read/write register used for temporarily storing data to be read/written to/from
the DDRAM or CGRAM. Data written into the DR is automatically written into DDRAM or
CGRAM by an internal operation of the display controller.
The DR is also used to store data when reading out data from DDRAM or CGRAM. When
address information is written into IR, data is read out from DDRAM or CGRAM to DR by
an internal operation. Data transfer is then completed by reading the DR.
After performing a read from the DR, data in the DDRAM or CGRAM at the next address is
sent to the DR for the next read cycle. The register select (RS) signal determines which of
these two registers is selected.
Table 4.1
RS
0
1
Selection of Registers
R/W
Function
0 Instruction Write operation (MPU writes instruction code to IR)
1 Read Busy flag (DB7) and Address Counter (DB0 to DB6)
0 Data Write operation (MPU writes data to DR)
1 Data Read operation (MPU reads data from DR)
4.2 Busy Flag (BF)
When the busy flag is high or 1the module is performing an internal operation and the
next instruction will not be accepted. The busy flag outputs to DB7 when RS = 0 and a
read operation is performed. The next instruction must not be written until ensuring that the
busy flag is low or 0.
4.3 Address Counter (AC)
The address counter (AC) assigns addresses to the DDRAM and the CGRAM.
When the address of an instruction is written into the IR, the address information is sent
from the IR to the AC. The selection of either DDRAM or CGRAM is also determined
concurrently by the same instruction. After writing into or reading from the DDRAM or
CGRAM the address counter (AC) is automatically increased by 1 or decreased by 1
(determined by the I/D bit in the Entry Mode Setcommand). AC contents are output to
DB0 to DB6 when RS = 0 and a read operation is performed.

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