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CAT93C57LE 데이터시트 PDF




Catalyst Semiconductor에서 제조한 전자 부품 CAT93C57LE은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 CAT93C57LE 자료 제공

부품번호 CAT93C57LE 기능
기능 2K-Bit Microwire Serial EEPROM
제조업체 Catalyst Semiconductor
로고 Catalyst Semiconductor 로고


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CAT93C57LE 데이터시트, 핀배열, 회로
CAT93C56/57 (Die Rev. E)
2K-Bit Microwire Serial EEPROM
FEATURES
ALOGEN FR
LEA D F REETM
I High speed operation: 1MHz
I Low power CMOS technology
I 1.8 to 6.0 volt operation
I Selectable x8 or x16 memory organization
I Self-timed write cycle with auto-clear
I Hardware and software write protection
I Power-up inadvertant write protection
I 1,000,000 Program/erase cycles
I 100 year data retention
I Commercial, industrial and automotive
temperature ranges
I Sequential read
I “Green” package option available
DESCRIPTION
The CAT93C56/57 are 2K-bit Serial EEPROM memory
devices which are configured as either registers of 16
bits (ORG pin at VCC) or 8 bits (ORG pin at GND). Each
register can be written (or read) serially by using the
DI (or DO) pin. The CAT93C56/57 are manufactured
using Catalyst’s advanced CMOS EEPROM floating
gate technology. The devices are designed to endure
1,000,000 program/erase cycles and has a data reten-
tion of 100 years. The devices are available in 8-pin DIP,
8-pin SOIC, 8-pin TSSOP and 8-pad TDFN packages.
PIN CONFIGURATION
DIP Package (P, L)
CS 1
SK 2
DI 3
DO 4
8 VCC
7 NC
6 ORG
5 GND
SOIC Package (J,W)
NC
VCC
CS
SK
1
2
3
4
8 ORG
7 GND
6 DO
5 DI
SOIC Package (S,V)
CS 1
SK 2
DI 3
DO 4
8 VCC
7 NC
6 ORG
5 GND
SOIC Package (K,X)
CS 1
SK 2
DI 3
DO 4
8 VCC
7 NC
6 ORG
5 GND
TSSOP Package (U,Y)
CS 1
SK 2
DI 3
DO 4
8 VCC
7 NC
6 ORG
5 GND
TDFN Package (RD4, ZD4)
VCC 8
NC 7
ORG 6
GND 5
1 CS
2 SK
3 DI
4 DO
Bottom View
FUNCTIONAL SYMBOL
VCC
ORG
CS
SK
NC
DI
DO
GND
PIN FUNCTIONS
Pin Name
CS
Function
Chip Select
SK Clock Input
DI Serial Data Input
DO Serial Data Output
VCC
GND
+1.8 to 6.0V Power Supply
Ground
ORG
Memory Organization
NC No Connection
Note: When the ORG pin is connected to VCC, the x16 organiza-
tion is selected. When it is connected to ground, the x8 pin is
selected. If the ORG pin is left unconnected, then an internal pullup
device will select the x16 organization.
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice.
Doc. No. 1088, Rev. M




CAT93C57LE pdf, 반도체, 판매, 대치품
CAT93C56/57
POWER-UP TIMING (1)(2)
Symbol
tPUR
tPUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max
1
1
Units
ms
ms
A.C. TEST CONDITIONS
Input Rise and Fall Times
50ns
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
0.4V to 2.4V
0.8V, 2.0V
0.2VCC to 0.7VCC
0.5VCC
4.5V VCC 5.5V
4.5V VCC 5.5V
1.8V VCC 4.5V
1.8V VCC 4.5V
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
(3) The input levels and timing reference points are shown in AC Test Conditionstable.
DEVICE OPERATION
The CAT93C56/57 is a 2048-bit nonvolatile memory
intended for use with industry standard microproces-
sors. The CAT93C56/57 can be organized as either
registers of 16 bits or 8 bits. When organized as X16,
seven 10-bit instructions for 93C57; seven 11-bit
instructions for 93C56 control the reading, writing and
erase operations of the device. When organized as X8,
seven 11-bit instructions for 93C57; seven 12-bit in-
structions for 93C56 control the reading, writing and
erase operations of the device. The CAT93C56/57
operates on a single power supply and will generate
on chip, the high voltage required during any write
operation.
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin is normally in a high impedance state except when
reading data from the device, or when checking the
ready/busy status after a write operation.
The ready/busy status can be determined after the start
of a write operation by selecting the device (CS high)
and polling the DO pin; DO low indicates that the
write operation is not completed, while DO high indi-
cates that the device is ready for the next instruction. If
necessary, the DO pin may be placed back into a high
impedance state during chip select by shifting a dummy
1into the DI pin. The DO pin will enter the high
impedance state on the falling edge of the clock (SK).
Placing the DO pin into the high impedance state is
recommended in applications where the DI pin and the
DO pin are to be tied together to form a common DI/O
pin.
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 7-bit address
(93C57)/ 8-bit address (93C56) (an additional bit when
organized X8) and for write operations a 16-bit data field
(8-bit for X8 organizations).
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C56/
57 will come out of the high impedance state and, after
sending an initial dummy zero bit, will begin shifting out
the data addressed (MSB first). The output data bits will
toggle on the rising edge of the SK clock and are stable
after the specified time delay (tPD0 or tPD1).
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of tCSMIN. The falling edge of CS will start the
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C56/57 can be determined by selecting the device
and polling the DO pin. Since this device features Auto-
Clear before write, it is NOT necessary to erase a
memory location before it is written into.
Doc. No. 1088, Rev. M
4

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CAT93C57LE 전자부품, 판매, 대치품
Figure 5. EWEN/EWDS Instruction Timing
SK
CS
DI
1 00
*
* ENABLE=11
DISABLE=00
CAT93C56/57
STANDBY
Figure 6. ERAL Instruction Timing
SK
CS
DI
1
00
10
HIGH-Z
DO
Figure 7. WRAL Instruction Timing
SK
CS
DI
1
000
1
DO
STATUS VERIFY
tCS
STANDBY
tSV
BUSY
tEW
READY
tHZ
HIGH-Z
STATUS VERIFY STANDBY
DN D0
tCSMIN
tSV tHZ
BUSY
tEW
READY
HIGH-Z
7 Doc. No. 1088, Rev. M

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