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CAT93C8621 데이터시트 PDF




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부품번호 CAT93C8621 기능
기능 Supervisory Circuits with Microwire Serial CMOS E2PROM/ Precision Reset Controller and Watchdog Timer
제조업체 Catalyst Semiconductor
로고 Catalyst Semiconductor 로고


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CAT93C8621 데이터시트, 핀배열, 회로
Advanced Information
CAT93CXXXX (1K-16K)
Supervisory Circuits with Microwire Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer
FEATURES
s Watchdog Timer
s Programmable Reset Threshold
s Built-in Inadvertent Write Protection
—VCC Lock Out
s High Speed Operation: 3MHz
s Low Power CMOS Technology
s x 16 or x 8 Selectable Serial Memory
s Self-Timed Write Cycle with Auto-Clear
s Sequential Read
s Fast Nonvolatile Write Cycle: 3ms Max
DESCRIPTION
s Active High or Low Reset Outputs
—Precision Power Supply Voltage Monitoring
—5V, 3.3V and 3V options
s Hardware and Software Write Protection
s Power-Up Inadvertant Write Protection
s 1,000,000 Program/Erase Cycles
s 100 Year Data Retention
s Commercial, Industrial, and Automotive
Temperature Ranges
s 2.7-6.0 Volt Operation
s 16 Byte Page Mode
The CAT93CXXXX is a single chip solution to three
popular functions of EEPROM memory, precision reset
controller and watchdog timer. The serial EEPROM
memory of the 93CXXXX can be configured either by 16-
bits or by 8-bits. Each register can be written (or read)
by using the DI (or DO pin).
The reset function of the 93CXXXX protects the system
during brown out and power up/down conditions. During
system failure the watchdog timer feature protects the
microcontroller with a reset signal. Catalyst's advanced
CMOS technology substantially reduces device power
requirements. The 93CXXXX is available in 8-pin DIP, 8-
pin TSSOP or 8-pin SOIC packages. It is designed to
endure 1,000,000 program/erase cycles and has a data
retention of 100 years.
PIN CONFIGURATION
BLOCK DIAGRAM
93CX61X
93CX62X
93CX63X
CS 1
SK 2
DI 3
DO 4
8 VCC
CS 1
7 RESET(RESET) SK 2
6 ORG
DI 3
5 GND
DO 4
8 VCC
CS 1
7 RESET(RESET) SK 2
6 WDI
DI 3
5 GND
DO 4
8 VCC
7 RESET
6 RESET
5 GND
VCC
GND
PIN FUNCTIONS
ORG
MEMORY ARRAY
Pin Name
Function
CS
RESET/RESET
SK
DI
DO
Chip Select
Reset I/O
Clock Input
Serial Data Input
Serial Data Output
DATA
REGISTER
DI
MODE DECODE
CS LOGIC
VCC
GND
+2.7 to 6.0V Power Supply
Ground
CLOCK
SK GENERATOR
ORG
Memory Organization
Note: When the ORG pin is connected to VCC, the X16 organiza
tion is selected. When it is connected to ground, the X8 pin
is selected. If the ORG pin is left unconnected, then an
internal pullup device will select the X16 organization.
ADDRESS
DECODER
OUTPUT
BUFFER
DO
RESET Controller
High
Precision
WATCHDOG
Vcc Monitor
WDI RESET/RESET
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9-85




CAT93C8621 pdf, 반도체, 판매, 대치품
CAT93CXXXX
INSTRUCTION SET
Instruction Device Start Opcode
Type
Bit
Address
x8 x16
Data
x8 x16
READ
93C46XX
93C56XX(1)
93C66XX
93C57XX
93C86XX
1
1
1
1
1
10 A6–A0 A5-A0
10 A8–A0 A7-A0
10 A8–A0 A7-A0
10 A7-A0 A6-A0
10 A10-A0 A9-A0
ERASE
93C46XX
93C56XX(1)
93C66XX
93C57XX
93C86XX
1
1
1
1
1
11 A6–A0 A5-A0
11 A8–A0 A7-A0
11 A8–A0 A7-A0
11 A7-A0 A6-A0
11 A10-A0 A9-A0
WRITE
93C46XX
93C56XX(1)
93C66XX
93C57XX
93C86XX
1
1
1
1
1
01 A6–A0 A5-A0 D7-D0 D15-D0
01 A8–A0 A7-A0 D7-D0 D15-D0
01 A8–A0 A7-A0 D7-D0 D15-D0
01 A7-A0 A6-A0 D7-D0 D15-D0
01 A10-A0 A9-A0 D7-D0 D15-D0
EWEN
93C46XX
93C56XX
93C66XX
93C57XX
93C86XX
1
1
1
1
1
00
11XXXXX
11XXXX
00 11XXXXXXX 11XXXXXX
00 11XXXXXXX 11XXXXXX
00 11XXXXXX 11XXXXX
00 11XXXXXXXXX 11XXXXXXXX
EWDS
93C46XX
93C56XX
93C66XX
93C57XX
93C86XX
1
1
1
1
1
00
00XXXXX
00XXXX
00 00XXXXXXX 00XXXXXX
00 00XXXXXXX 00XXXXXX
00 00XXXXXX 00XXXXX
00 00XXXXXXXXX 00XXXXXXXX
ERAL
93C46XX
93C56XX
93C66XX
93C57XX
93C86XX
1
1
1
1
1
00
10XXXXX
10XXXX
00 10XXXXXXX 10XXXXXX
00 10XXXXXXX 10XXXXXX
00 10XXXXXX 10XXXXX
00 10XXXXXXXXX 10XXXXXXXX
WRAL
93C46XX
93C56XX
93C66XX
93C57XX
93C86XX
1
1
1
1
1
00 01XXXXX 01XXXX D7-D0 D15-D0
00 01XXXXXXX 01XXXXXX D7-D0 D15-D0
00 01XXXXXXX 01XXXXXX D7-D0 D15-D0
00 01XXXXXX 01XXXXX D7-D0 D15-D0
00 01XXXXXXXXX 01XXXXXXXX D7-D0 D15-D0
Advanced Information
Comments
Read Address AN–A0
Clear Address AN–A0
Write Address AN–A0
Write Enable
Write Disable
Clear All Addresses
Write All Addresses
Note:
(1) Address bit A8 for 256x8 ORG and A7 for 128x16 ORG are "Don't Care" bits, but must be kept at either a "1" or "0" for READ, WRITE and
ERASE commands.
Stock No. 21084-01 2/98
9-88

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CAT93C8621 전자부품, 판매, 대치품
Advanced Information
CAT93CXXXX
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93CXXXX
will come out of the high impedance state and, after
sending an initial dummy zero bit, will begin shifting out
the data addressed (MSB first). The output data bits will
toggle on the rising edge of the SK clock and are stable
after the specified time delay (tPD0 or tPD1)
For the 93CXXXX, after the initial data word has been
shifted out and CS remains asserted with the SK clock
continuing to toggle, the device will automatically incre-
ment to the next address and shift out the next data word
in a sequential READ mode. As long as CS is continu-
ously asserted and SK continues to toggle, the device
will keep incrementing to the next address automatically
until it reaches to the end of the address space, then
loops back to address 0. In the sequential READ mode,
only the initial data word is preceeded by a dummy zero
bit. All subsequent data words will follow without a
dummy zero bit.
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of tCSMIN. The falling edge of CS will start the
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93CXXXX can be determined by selecting the de-
vice and polling the DO pin. Since this device features
Auto-Clear before write, it is NOT necessary to erase a
memory location before it is written into.
Page Write
The 93CXXXX writes up to 16 bytes (8 words for x16
format) of data in a single write cycle, using the page
write operation. The page write operation is initiated in
the same manner as the byte (word for x16 format) write
operation. However, instead of terminating after the
initial byte (word for x16 format) is transmitted, the host
Figure 2. Sychronous Data Timing
tSKHI
SK
tDIS
DI VALID
tCSS
CS
DO
tSKLOW
VALID
tDIH
tCSH
tDIS
tPD0,tPD1
tCSMIN
DATA VALID
Figure 3. Read Instruction Timing
SK
1 11 1 111 11 1 1 1 1 1 1
CS
AN AN–1
DI
11
0
A0
Don't Care
HIGH-Z
DO
Dummy 0
D15 . . . D0
or
D7 . . . D0
Address + 1
D15 . . . D0
or
D7 . . . D0
Address + 2
D15 . . . D0
or
D7 . . . D0
Address + n
D15 . . .
or
D7 . . .
9-91
Stock No. 21084-01 2/98

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