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PDF HCPL0601 Data sheet ( Hoja de datos )
| Número de pieza | HCPL0601 | |
| Descripción | High Speed-10 MBit/s Logic Gate Optocouplers | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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HCPL0600, HCPL0601, HCPL0611,
HCPL0637, HCPL0638, HCPL0639
High Speed-10 MBit/s Logic Gate Optocouplers
April 2009
Single Channel: HCPL0600, HCPL0601, HCPL0611
Dual Channel: HCPL0637, HCPL0638, HCPL0639
Features
■ Compact SO8 package
■ Very high speed-10 MBit/s
■ Superior CMR
■ Logic gate output
■ Strobable output (single channel devices)
■ Wired OR-open collector
■ U.L. recognized (File # E90700)
■ IEC60747-5-2 approved (VDE option)
– HCPL0600, HCPL0601, HCPL0611 only
Applications
■ Ground loop elimination
■ LSTTL to TTL, LSTTL or 5-volt CMOS
■ Line receiver, data transmission
■ Data multiplexing
■ Switching power supplies
■ Pulse transformer replacement
■ Computer-peripheral interface
Description
The HCPL06XX optocouplers consist of an AlGaAS
LED, optically coupled to a very high speed integrated
photo-detector logic gate with a strobable output (single
channel devices). The devices are housed in a compact
small-outline package. This output features an open col-
lector, thereby permitting wired OR outputs. The
HCPL0600, HCPL0601 and HCPL0611 output consists
of bipolar transistors on a bipolar process while the
HCPL0637, HCPL0638, and HCPL0639 output consists
of bipolar transistors on a CMOS process for reduced
power consumption. The coupled parameters are guar-
anteed over the temperature range of -40°C to +85°C.
An internal noise shield provides superior common
mode rejection.
Package Dimensions
0.164 (4.16)
0.144 (3.66)
Pin 1
0.202 (5.13)
0.182 (4.63)
0.143 (3.63)
0.123 (3.13)
0.019 (0.48)
0.010 (0.25)
0.006 (0.16)
0.021 (0.53)
0.011 (0.28)
0.008 (0.20)
0.003 (0.08)
0.050 (1.27)
TYP
0.244 (6.19)
0.224 (5.69)
Lead Coplanarity : 0.004 (0.10) MAX
Note:
All dimensions are in inches (millimeters)
©2006 Fairchild Semiconductor Corporation
HCPL06XX Rev. 1.0.8
www.fairchildsemi.com
1 page  
Transfer Characteristics (TA = -40°C to +85°C unless otherwise specified.)
Symbol DC Characteristics
Test Conditions
Min.
IOH High Level Output Current
VOL Low Level Output Voltage
IFT Input Threshold Current
VCC = 5.5V, VO = 5.5 V, IF = 250µA,
VE = 2.0V(2)
VCC = 5.5V, IF = 5mA, VE = 2.0V,
IOL = 13mA(2)
VCC = 5.5V, VO = 0.6V, VE = 2.0V,
IOL = 13mA
Typ.*
Max.
100
0.6
5
Isolation Characteristics (TA = -40°C to +85°C unless otherwise specified.)
Symbol
Characteristics
Test Conditions
Min.
II-O Input-Output
Insulation Leakage Current
VISO
Withstand Insulation Test Voltage
RI-O Resistance (Input to Output)
CI-O Capacitance (Input to Output)
*All typical values are at VCC = 5 V, TA = 25°C
Relative humidity = 45%,
TA = 25°C, t = 5s,
VI-O = 3000 VDC(11)
RH < 50%, TA = 25°C,
II-O ≤ 2µA, t = 1 min.(11)
VI-O = 500V(11)
f = 1MHz(11)
3750
Typ.*
1012
0.6
Max.
1.0*
Unit
µA
V
mA
Unit
µA
VRMS
Ω
pF
Notes:
1. The VCC supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic
or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible
to the package VCC and GND pins of each device.
2. Enable Input – No pull up resistor required as the device has an internal pull up resistor.
3. tPLH – Propagation delay is measured from the 3.75mA level on the HIGH to LOW transition of the input current
pulse to the 1.5V level on the LOW to HIGH transition of the output voltage pulse.
4. tPHL – Propagation delay is measured from the 3.75mA level on the LOW to HIGH transition of the input current
pulse to the 1.5V level on the HIGH to LOW transition of the output voltage pulse.
5. tr – Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse.
6. tf – Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse.
7. tELH – Enable input propagation delay is measured from the 1.5V level on the HIGH to LOW transition of the input
voltage pulse to the 1.5V level on the LOW to HIGH transition of the output voltage pulse.
8. tEHL – Enable input propagation delay is measured from the 1.5V level on the LOW to HIGH transition of the input
voltage pulse to the 1.5V level on the HIGH to LOW transition of the output voltage pulse.
9. CMH – The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high
state (i.e., VOUT > 2.0V). Measured in volts per microsecond (V/µs).
10. CML – The maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the low
output state (i.e., VOUT < 0.8V). Measured in volts per microsecond (V/µs).
11. Device considered a two-terminal device: Pins 1, 2, 3 and 4 shorted together, and Pins 5, 6, 7 and 8 shorted
together.
©2006 Fairchild Semiconductor Corporation
HCPL06XX Rev. 1.0.8
5
www.fairchildsemi.com
5 Page 
Pulse Gen.
tf = tr = 5 ns
ZO = 50 Ω
1
Input
Monitor
(IF)
47Ω
2
3
4
VCC 8
7
.1µf
Bypass
6
GND 5
+5V
Pulse Gen.
ZO = 50 Ω
tf = tr = 5 ns
IF
Input
RL Monitoring
Node
Output
(VO)
CL
RM
Test Circuit for HCPL0600,
HCPL0601 and HCPL0611
Dual Channel
1 VCC 8
27
36
45
GND
+5 V
RL
0.1µF
Bypass
Output VO
Monitoring
Node
CL*
Input
(I F)
tPHL
Output
(VO)
Output
(VO)
Test Circuit for HCPL0637,
HCPL0638 and HCPL0639
tf
I F = 7.5 mA
I F = 3.75 mA
tPLH
90%
10 %
1.5 V
tr
Fig. 20 Test Circuit and Waveforms for tPLH, tPHL, tr and tf.
Pulse
Generator
tr = 5ns
ZO = 50Ω
1
7.5 mA
2
3
4
Input
Monitor
(VE)
+5V
VCC
8
7
.1µf
bypass
6
5
GND
RL
Output
(VO)
CL
Input
(VE )
tEHL
Output
(VO)
Fig. 21 Test Circuit tEHL and tELH.
t ELH
3.0 V
1.5 V
1.5 V
©2006 Fairchild Semiconductor Corporation
HCPL06XX Rev. 1.0.8
11
www.fairchildsemi.com
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet HCPL0601.PDF ] | |
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