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MT16HTF25664HY 데이터시트 PDF




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부품번호 MT16HTF25664HY 기능
기능 2GB DDR2 SDRAM SODIMM
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MT16HTF25664HY 데이터시트, 핀배열, 회로
1GB, 2GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Features
DDR2 SDRAM SODIMM
MT16HTF12864HY – 1GB
MT16HTF25664HY – 2GB
Features
200-pin, small-outline dual in-line memory module
(SODIMM)
Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300, or PC2-6400
1GB (128 Meg x 64) or 2GB (256 Meg x 64)
VDD = VDDQ 1.8V
VDDSPD = 1.7–3.6V
JEDEC-standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
4n-bit prefetch architecture
Multiple internal device banks for concurrent opera-
tion
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency - 1 tCK
Programmable burst lengths (BL): 4 or 8
Adjustable data-output drive strength
64ms, 8192-cycle refresh
On-die termination (ODT)
Serial presence detect (SPD) with EEPROM
Gold edge contacts
Dual rank
Figure 1: 200-Pin SODIMM (MO-224 R/C E)
Module height: 30mm (1.18in)
Options
Operating temperature
Commercial (0°C TA +70°C)
Industrial (–40°C TA +85°C)1
Package
200-pin DIMM (lead-free)
Frequency/CL2
2.5ns @ CL = 5 (DDR2-800)
2.5ns @ CL = 6 (DDR2-800)
3ns @ CL = 5 (DDR2-667)
3.75ns @ CL = 4 (DDR2-533)
5.0ns @ CL = 3 (DDR2-400)3
Marking
None
I
Y
-80E
-800
-667
-53E
-40E
Notes:
1. Contact Micron for industrial temperature
module offerings.
2. CL = CAS (READ) latency.
3. Not recommended for new designs.
Table 1: Key Timing Parameters
Speed
Grade
-80E
-800
-667
-53E
-40E
Industry
Nomenclature
PC2-6400
PC2-6400
PC2-5300
PC2-4200
PC2-3200
CL = 6
800
800
Data Rate (MT/s)
CL = 5
CL = 4
800 533
667 533
667 553
553
400
CL = 3
400
400
400
400
400
tRCD
(ns)
12.5
15
15
15
15
tRP
(ns)
12.5
15
15
15
15
tRC
(ns)
55
55
55
55
55
PDF: 09005aef818e4054
htf16c128_256x64h.pdf - Rev. D 3/10 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2004 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.




MT16HTF25664HY pdf, 반도체, 판매, 대치품
1GB, 2GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Pin Descriptions
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR2
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.
Table 6: Pin Descriptions
Symbol
Ax
Type
Input
BAx
CKx,
CK#x
CKEx
DMx,
Input
Input
Input
Input
ODTx
Input
Par_In
RAS#, CAS#, WE#
RESET#
S#x
SAx
SCL
CBx
DQx
DQSx,
DQS#x
Input
Input
Input
Input
Input
Input
I/O
I/O
I/O
Description
Address inputs: Provide the row address for ACTIVE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments Table for density-specific
addressing information.
Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, and MR3) is loaded during the LOAD MODE command.
Clock: Differential clock inputs. All control, command, and address input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui-
try and clocks on the DDR2 SDRAM.
Data mask (x8 devices only): DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH, along with that input data, during a write ac-
cess. Although DM pins are input-only, DM loading is designed to match that of the
DQ and DQS pins.
On-die termination: Enables (registered HIGH) and disables (registered LOW) termi-
nation resistance internal to the DDR2 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This
signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z.
Chip select: Enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs: Used to configure the SPD EEPROM address range on the I2C
bus.
Serial clock for SPD EEPROM: Used to synchronize communication to and from the
SPD EEPROM on the I2C bus.
Check bits. Used for system error detection and correction.
Data input/output: Bidirectional data bus.
Data strobe: Travels with the DQ and is used to capture DQ at the DRAM or the con-
troller. Output with read data; input with write data for source synchronous opera-
tion. DQS# is only used when differential data strobe mode is enabled via the LOAD
MODE command.
PDF: 09005aef818e4054
htf16c128_256x64h.pdf - Rev. D 3/10 EN
4 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2004 Micron Technology, Inc. All rights reserved.

4페이지










MT16HTF25664HY 전자부품, 판매, 대치품
1GB, 2GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
General Description
General Description
DDR2 SDRAM modules are high-speed, CMOS dynamic random access memory mod-
ules that use internally configured 4 or 8-bank DDR2 SDRAM devices. DDR2 SDRAM
modules use DDR architecture to achieve high-speed operation. DDR2 architecture is
essentially a 4n-prefetch architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM
module effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the
internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data trans-
fers at the I/O pins.
DDR2 modules use two sets of differential signals: DQS, DQS# to capture data and CK
and CK# to capture commands, addresses, and control signals. Differential clocks and
data strobes ensure exceptional noise immunity for these signals and provide precise
crossing points to capture input signals. A bidirectional data strobe (DQS, DQS#) is trans-
mitted externally, along with data, for use in data capture at the receiver. DQS is a
strobe transmitted by the DDR2 SDRAM device during READs and by the memory con-
troller during WRITEs. DQS is edge-aligned with data for READs and center-aligned
with data for WRITEs.
DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com-
mands (address and control signals) are registered at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
Serial Presence-Detect EEPROM Operation
DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the mod-
ule type and various SDRAM organizations and timing parameters. The remaining 128
bytes of storage are available for use by the customer. System READ/WRITE operations
between the master (system logic) and the slave EEPROM device occur via a standard
I2C bus using the DIMM’s SCL (clock) SDA (data), and SA (address) pins. Write protect
(WP) is connected to VSS, permanently disabling hardware write protection.
PDF: 09005aef818e4054
htf16c128_256x64h.pdf - Rev. D 3/10 EN
7 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2004 Micron Technology, Inc. All rights reserved.

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2GB DDR2 SDRAM SODIMM

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