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MT18HTF12872P 데이터시트 PDF




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부품번호 MT18HTF12872P 기능
기능 1GB DDR2 SDRAM Registered DIMM
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MT18HTF12872P 데이터시트, 핀배열, 회로
512MB, 1GB, 2GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Features
DDR2 SDRAM Registered DIMM (RDIMM)
MT18HTF6472 – 512MB
MT18HTF12872(P) – 1GB
MT18HTF25672(P) – 2GB
For component data sheets, refer to Micron's Web site: www.micron.com
Features
• 240-pin, registered dual in-line memory module
• Fast data transfer rates: PC2-3200, PC2-4200, PC2-
5300, or PC2-6400
• Supports ECC error detection and correction
• VDD = VDDQ = +1.8V
• VDDSPD = +1.7V to +3.6V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4n-bit prefetch architecture
• Single rank
• Multiple internal device banks for concurrent
operation
• Programmable CAS# latency (CL)
• Posted CAS# additive latency (AL)
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts
Figure 1:
240-Pin RDIMM (MO-237
R/C C–Non-Parity, R/C H–Parity)
PCB height: 30mm (1.18in)
Options
• Parity3
• Operating temperature1
Commercial (0°C TA +70°C)
Industrial (–40°C TA +85°C)
• Package
240-pin DIMM (Pb-free)
• Frequency/CAS latency2
2.5ns @CL = 5 (DDR2-800)3
2.5ns @ CL = 6 (DDR2-800)3
3.0ns @ CL = 5 (DDR2-667)3
3.75ns @ CL = 4 (DDR2-533)
5.0ns @ CL = 3 (DDR2-400)
• PCB height
30mm (1.18in)
Marking
P
None
I
Y
-80E
-800
-667
-53E
-40E
Notes: 1. Contact Micron for industrial temperature
module offerings.
2. CL = CAS (READ) latency; registered mode
will add one clock cycle to CL.
3. Not available in 512MB density.
Table 1: Key Timing Parameters
Speed
Grade
-80E
-800
-667
-53E
-40E
Industry
Nomenclature
PC2-6400
PC2-6400
PC2-5300
PC2-4200
PC2-3200
CL = 6
800
Data Rate (MT/s)
CL = 5
800
667
667
CL = 4
533
533
533
533
400
CL = 3
400
400
400
tRCD
(ns)
12.5
15
15
15
15
tRP
(ns)
tRC
(ns)
12.5 55
15 55
15 55
15 55
15 55
PDF: 09005aef80e5e752/Source: 09005aef80e5e626
HTF18C64_128_256x72.fm - Rev. E 3/07 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.




MT18HTF12872P pdf, 반도체, 판매, 대치품
512MB, 1GB, 2GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Pin Assignments and Descriptions
Table 7: Pin Descriptions
Symbol
Type
Description
ODT0
Input On-die termination: ODT (registered HIGH) enables termination resistance internal to the
(SSTL_18) DDR2 SDRAM. When enabled, ODT is only applied to the following pins: DQ, DQS, DQS#,
and CB. The ODT input will be ignored if disabled via the LOAD MODE command.
CK0, CK0#
Input Clock: CK and CK# are differential clock inputs. All address and control input signals are
(SSTL_18) sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data
(DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.
CKE0
Input Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates
(SSTL_18) clocking circuitry on the DDR2 SDRAM.
S0# Input Chip select: S# enables (registered LOW) and disables (registered HIGH) the command
(SSTL_18) decoder.
RAS#, CAS#,
WE#
Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
(SSTL_18) entered.
BA0, BA1
(512MB, 1GB)
BA0, BA1, BA2
(2GB)
Input
(SSTL_18)
Bank address inputs: BA0–BA1/BA2 define the device bank to which an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied. BA0–BA1/BA2 define which mode
register, including MR, EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE
command.
A0–A12
(512MB)
A0–A13
(1GB, 2GB)
Input
(SSTL_18)
Address inputs: Provide the row address for ACTIVE commands, and the column address
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0–BA1/BA2) or all device banks (A10 HIGH). The address inputs also provide
the op-code during a LOAD MODE command.
PAR_IN
Input Parity bit for the address and control bus.
(SSTL_18)
SCL Input Serial clock for presence-detect: SCL is used to synchronize the presence-detect data
transfer to and from the module.
SA0–SA2
Input
Presence-detect address inputs: These pins are used to configure the presence-detect
device.
RESET#
Input Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal can be
(LVCMOS) used during power-up to ensure that CKE is LOW and DQs are High-Z.
DQS0–DQS17,
I/O Data strobe: Output with read data, input with write data for source synchronous
DQS0#–DQS17# (SSTL_18) operation. Edge-aligned with read data, center-aligned with write data. DQS# is only used
when differential data strobe mode is enabled via the LOAD MODE command.
DQ0–DQ63
I/O Data input/output: Bidirectional data bus.
(SSTL_18)
CB0–CB7
I/O Check bits.
(SSTL_18)
SDA I/O Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and
data into and out of the presence-detect portion of the module.
ERR_OUT
Output Parity error found on the address and control bus.
(open drain)
VDD/VDDQ
Supply Power supply: 1.8V ±0.1V.
VREF
Supply SSTL_18 reference voltage.
VSS Supply Ground.
VDDSPD
Supply Serial EEPROM positive power supply: +1.7V to +3.6V.
NC – No connect: These pins should be left unconnected.
DNU
– Do not use.
PDF: 09005aef80e5e752/Source: 09005aef80e5e626
HTF18C64_128_256x72.fm - Rev. E 3/07 EN
4 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.

4페이지










MT18HTF12872P 전자부품, 판매, 대치품
512MB, 1GB, 2GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed in Table 8 may cause permanent damage to the
module. This is a stress rating only, and functional operation of the module at these or
any other conditions above those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
Table 8: Absolute Maximum Ratings
Symbol
VDD/VDDQ
VIN, VOUT
II
IOZ
IVREF
TA
TC1
Parameter
VDD supply voltage relative to VSS
Voltage on any pin relative to VSS
Input leakage current; Any input 0V VIN VDD;
VREF input 0V VIN 0.95V; (All other pins not under
test = 0V)
Output leakage current; 0V VOUT VDDQ; DQs and
ODT are disabled
VREF leakage current; VREF = Valid VREF level
Module ambient operating temperature
DDR2 SDRAM component case operating
temperature2
Command/address,
RAS#, CAS#, WE#, S#,
CKE, ODT, BA
CK, CK#
DQ, DQS, DQS#
Commercial
Industrial
Commercial
Industrial
Min
–0.5
–0.5
–5
–250
–5
–36
0
–40
0
–40
Max
+2.3
+2.3
+5
+250
+5
+36
+70
+85
+85
+85
Units
V
V
µA
µA
µA
°C
°C
°C
°C
Notes:
1. The refresh rate is required to double when 85°C < TC 95°C.
2. For further information, refer to technical note TN-00-08: Thermal Applications, available
on Micron’s Web site.
Input Capacitance
Micron encourages designers to simulate the performance of the module to achieve
optimum values. Simulations are significantly more accurate and realistic than a gross
estimation of module capacitance when inductance and delay parameters associated
with trace lengths are used in simulations. JEDEC modules are currently designed using
simulations to close timing budgets.
Component AC Timing and Operating Conditions
Recommended AC operating conditions are given in the DDR2 component data sheets.
Component specifications are available on Micron’s Web site. Module speed grades
correlate with component speed grades as shown in Table 9.
Table 9: Module and Component Speed Grades
Module Speed Grade
-80E
-800
-667
-53E
-40E
Component Speed Grade
-25E
-25
-3
-37E
-5E
PDF: 09005aef80e5e752/Source: 09005aef80e5e626
HTF18C64_128_256x72.fm - Rev. E 3/07 EN
7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.

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MT18HTF12872

1GB DDR2 SDRAM Registered DIMM

Micron
Micron
MT18HTF12872P

1GB DDR2 SDRAM Registered DIMM

Micron
Micron

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