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부품번호 MT18VDDT6472A 기능
기능 512MB DDR SDRAM UNBUFFERED DIMM
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MT18VDDT6472A 데이터시트, 핀배열, 회로
256MB, 512MB, 1GB (x72, ECC, DR), PC3200
184-PIN DDR SDRAM UDIMM
DDR SDRAM
UNBUFFERED DIMM
MT18VDDT3272A – 256MB
MT18VDDT6472A – 512MB
MT18VDDT12872A – 1GB
For the latest data sheet, please refer to the MicronWeb
site: www.micron.com/products/modules
Features
• 184-pin dual in-line memory module (DIMM)
• Fast data transfer rates: PC3200
• CAS Latency 3
• Utilizes 400 MT/s DDR SDRAM components
• Supports ECC error detection and correction
• 256MB (32 Meg x 72), 512MB (64 Meg x 72), and 1GB
(128 Meg x 72)
• VDD = VDDQ = +2.6V
• VDDSPD = +2.3V to +3.6V
• 2.6V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/received
with data—i.e., source-synchronous data capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 15.6µs (256MB), 7.8125µs (512MB, 1GB) maximum
average periodic refresh interval
• Serial Presence Detect (SPD) with EEPROM
• Programmable READ CAS latency
• Gold edge contacts
Figure 1: 184-Pin DIMM (MO-206)
1.25in. (31.75mm)
OPTIONS
• Package
184-pin DIMM (Standard)
184-pin DIMM (Lead-free)
• Memory Clock/Speed, CAS Latency
5ns (200MHz), 400MT/s, CL = 3
• PCB
Standard 1.25in. (31.75mm)
MARKING
G
Y
-40B
Table 1: Address Table
Refresh Count
Row Addressing
Device Bank Addressing
Device Configuration
Column Addressing
Module Rank Addressing
256MB
4K
4K (A0–A11)
4 (BA0, BA1)
128Mb (16 Meg x 8)
1K (A0–A9)
2 (S0#, S1#)
512MB
8K
8K (A0–A12)
4 (BA0, BA1)
256Mb (32 Meg x 8)
1K (A0–A9)
2 (S0#, S1#)
1GB
8K
8K (A0–A12)
4 (BA0, BA1)
512Mb (64 Meg x 8)
2K (A0–A9, A11)
2 (S0#, S1#)
pdf: 09005aef80814e61, source: 09005aef80a43eed
DDA18C32_64_128x72AG.fm - Rev. E 9/04 EN
1
©2004 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.




MT18VDDT6472A pdf, 반도체, 판매, 대치품
256MB, 512MB, 1GB (x72, ECC, DR), PC3200
184-PIN DDR SDRAM UDIMM
Table 5: Pin Descriptions
Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information
PIN NUMBERS
63, 65, 154
16, 17, 75, 76, 137, 138
SYMBOL
WE#, CAS#, RAS#
CK0, CK0#, CK1,
CK1#, CK2, CK2#
21, 111
CKE0, CKE1
157, 158
S0#, S1#
52, 59
BA0, BA1
27, 29, 32, 37, 41, 43, 48,
115 (512MB, 1GB), 118, 122,
125, 130, 141
A0–A11
(256MB)
A0–A12
(512MB, 1GB)
44, 45, 49, 51, 134, 135, 142,
144
5, 14, 25, 36, 47, 56, 67, 78,
86
CB0–CB7
DQS0–DQS8
97, 107, 119, 129, 140, 149,
159, 169, 177
DM0DM8
TYPE
Input
Input
Input
Input
Input
Input
Input/
Output
Input/
Output
Input
DESCRIPTION
Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Clock: CK, CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the
positive edge of CK,and negative edge of CK#. Output data
(DQs and DQS) is referenced to the crossings of CK and CK#.
Clock Enable: CKE HIGH activates and CKE LOW deactivates
the internal clock, input buffers and output drivers. Taking
CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operations (all device banks idle), or ACTIVE POWER-
DOWN (row ACTIVE in any device bank). CKE is synchronous
for POWER-DOWN entry and exit, and for SELF REFRESH entry.
CKE is asynchronous for SELF REFRESH exit and for disabling
the outputs. CKE must be maintained HIGH throughout read
and write accesses. Input buffers (excluding CK, CK# and CKE)
are disabled during POWER-DOWN. Input buffers (excluding
CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input
but will detect an LVCMOS LOW level after VDD is applied and
until CKE is first brought HIGH. After CKE has been brought
HIGH, it is an SSTL_2 input only.
Chip Selects: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
Bank Address: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address Inputs: Provide the row address for ACTIVE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded
during the LOAD MODE REGISTER command.
Check bits.
Data Strobe: Output with READ data, input with WRITE data.
DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.
Data Write Mask: DM LOW allows WRITE operation. DM HIGH
blocks WRITE operation. DM lines do not affect READ
operation.
pdf: 09005aef80814e61, source: 09005aef80a43eed
DDA18C32_64_128x72AG.fm - Rev. E 9/04 EN
4 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.

4페이지










MT18VDDT6472A 전자부품, 판매, 대치품
256MB, 512MB, 1GB (x72, ECC, DR), PC3200
184-PIN DDR SDRAM UDIMM
General Description
The MT18VDDT3272A, MT18VDDT6472, and
MT18VDDT12872 are high-speed CMOS, dynamic
random-access, 256MB, 512MB, and 1GB memory
modules organized in x72 (ECC) configuration. DDR
SDRAM modules use internally configured quad-bank
DDR SDRAM devices.
DDR SDRAM modules use a double data rate archi-
tecture to achieve high-speed operation. Double data
rate architecture is essentially a 2n-prefetch architec-
ture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or
write access for the DDR SDRAM module effectively
consists of a single 2n-bit wide, one-clock-cycle data
transfer at the internal DRAM core and two corre-
sponding n-bit wide, one-half-clock-cycle data trans-
fers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at
the receiver. DQS is an intermittent strobe transmitted
by the DDR SDRAM during READs and by the memory
controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for
WRITEs.
DDR SDRAM modules operate from differential
clock inputs (CK and CK#); the crossing of CK going
HIGH and CK# going LOW will be referred to as the
positive edge of CK. Commands (address and control
signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and out-
put data is referenced to both edges of DQS, as well as
to both edges of CK.
Read and write accesses to DDR SDRAM modules
are burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed (BA0, BA1 select devices bank; A0–A11 select
device row for 256MB, A0–A12 select device row for
512MB and 1GB). The address bits registered coinci-
dent with the READ or WRITE command are used to
select the device bank and the starting device column
location for the burst access.
DDR SDRAM modules provide for programmable
READ or WRITE burst lengths of 2, 4, or 8 locations. An
auto precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end of
the burst access.
The pipelined, multibank architecture of DDR
SDRAM modules allows for concurrent operation,
thereby providing high effective bandwidth by hiding
row precharge and activation time.
An auto refresh mode is provided, along with a
power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All out-
puts are SSTL_2, Class II compatible. For more
information regarding DDR SDRAM operation, refer to
the 128Mb, 256Mb, or 512Mb DDR SDRAM compo-
nent data sheets.
Serial Presence-Detect Operation
DDR SDRAM modules incorporate serial presence-
detect (SPD). The SPD function is implemented using
a 2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various SDRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for
use by the customer. System READ/WRITE operations
between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard I2C bus
using the DIMM’s SCL (clock) and SDA (data) signals,
together with SA (2:0), which provide eight unique
DIMM/EEPROM addresses. Write protect (WP) is tied
to ground on the module, permanently disabling hard-
ware write protect.
Mode Register Definition
The mode register is used to define the specific
mode of operation of DDR SDRAM devices. This defi-
nition includes the selection of a burst length, a burst
type, a CAS latency and an operating mode, as shown
in Figure 4, Mode Register Definition Diagram, on
page 8. The mode register is programmed via the
MODE REGISTER SET command (with BA0 = 0 and
BA1 = 0) and will retain the stored information until it
is programmed again or the device loses power (except
for bit A8, which is self-clearing).
Reprogramming the mode register will not alter the
contents of the memory, provided it is performed cor-
rectly. The mode register must be loaded (reloaded)
when all device banks are idle and no bursts are in
progress, and the controller must wait the specified
time before initiating the subsequent operation. Vio-
lating either of these requirements will result in
unspecified operation.
Mode register bits A0–A2 specify the burst length,
A3 specifies the type of burst (sequential or inter-
leaved), A4–A6 specify the CAS latency, and A7–A11
(256MB) or A7–A12 (512MB and 1GB) specify the oper-
ating mode.
pdf: 09005aef80814e61, source: 09005aef80a43eed
DDA18C32_64_128x72AG.fm - Rev. E 9/04 EN
7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.

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MT18VDDT6472A

512MB DDR SDRAM UNBUFFERED DIMM

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