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MT18VDVF6472D 데이터시트 PDF




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부품번호 MT18VDVF6472D 기능
기능 512MB DDR SDRAM VLP Registered DIMM
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MT18VDVF6472D 데이터시트, 핀배열, 회로
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
Features
DDR SDRAM VLP Registered DIMM
MT18VDVF6472D – 512MB
MT18VDVF12872D – 1GB
For the latest data sheet, refer to Micron’s Web site: www.micron.com/products/modules
Features
• 184-pin, very low profile dual in-line memory
module (VLP DIMM)
• Fast data transfer rates: PC2100 or PC2700
• Utilizes 266 MT/s and 333 MT/s DDR SDRAM
components
• Registered inputs with one-clock delay
• Phase-lock loop (PLL) clock driver to reduce loading
• Supports ECC error detection and correction
• 512MB (64 Meg x 72) and 1GB (128 Meg x 72)
• VDD = VDDQ = +2.5V
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data—i.e., source-synchronous data
capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto refresh and self refresh modes
• 7.8125µs maximum average periodic refresh
interval
• Serial presence detect (SPD) with EEPROM
• Programmable READ CAS latency
• Gold edge contacts
• Dual rank
Figure 1: 184-Pin VLP DIMM (MO-206)
Very Low Profile Height 0.72in (18.29mm)
Options
Marking
• Package
184-pin DIMM (standard)
184-pin DIMM (lead-free)1
• Memory clock, speed, CAS latency2
6ns (166MHz), 333 MT/s, CL = 2.5
7.5ns (133 MHz), 266 MT/s, CL = 2
7.5ns (133 MHz), 266 MT/s, CL = 2
7.5ns (133 MHz), 266 MT/s, CL = 2.5
• PCB height
Very Low-Profile 0.72in (18.29mm)1
G
Y
-335
-2621
-26A1
-265
Notes:1. Contact Micron for product availability.
2. CL = CAS (READ) latency; registered mode
adds one clock cycle to CL.
PDF: 09005aef81c73825/Source: 09005aef81c73837
DVF18C64_128x72D_1.fm - Rev. A 8/05 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.




MT18VDVF6472D pdf, 반도체, 판매, 대치품
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
List of Figures
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
Figure 11:
Figure 12:
Figure 13:
Figure 14:
Figure 15:
Figure 16:
184-Pin VLP DIMM (MO-206) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Very Low Profile DIMM Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Mode Register Definition Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
CAS Latency Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Extended Mode Register Definition Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Derating Data Valid Window (tQH - tDQSQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Pull-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Pull-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Initialization Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Component Case Temperature vs. Air Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Data Validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Definition of Start and Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Acknowledge Response From Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
SPD EEPROM Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
184-Pin VLP RDIMM Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
PDF: 09005aef81c73825/Source: 09005aef81c73837
DVF18C64_128x72DLOF.fm - Rev. A 8/05 EN
4 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, 2004, 2005 Micron Technology, Inc. All rights reserved.

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MT18VDVF6472D 전자부품, 판매, 대치품
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
Pin Assignments and Descriptions
Table 4:
Pin Descriptions
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 6 for more information
Pin Numbers
10
63, 65, 154
137, 138
21,111
157, 158
52, 59
27, 29, 32, 37, 41, 43, 48,
115, 118, 122, 125, 130,
141
97, 107, 119, 129, 140,
149, 159, 169, 177
5, 14, 25, 36, 47, 56, 67,
78, 86
44, 45, 49, 51, 134, 135,
142, 144
Symbol
RESET#
WE#, CAS#, RAS#
CK0, CK0#
CKE0, CKE1
S0#, S1#
BA0, BA1
A0–A12
DM0–DM8
DQS0–DQS8
CB0–CB7
Type
Description
Input Asynchronously forces all registered ouputs LOW when RESET#
is LOW. This signal can be used during power-up to ensure CKE
is LOW and DQs are High-Z.
Input Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Input
Clock: CK, CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK,and negative edge of CK#. Output data (DQ and
DQS) is referenced to the crossings of CK and CK#.
Input
Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE
LOW provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all device banks idle), or ACTIVE POWER-DOWN
(row ACTIVE in any device bank). CKE is synchronous for
POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE
is asynchronous for SELF REFRESH exit and for disabling the
outputs. CKE must be maintained HIGH throughout read and
write accesses. Input buffers (excluding CK, CK# and CKE) are
disabled during POWER-DOWN. Input buffers (excluding CKE)
are disabled during SELF REFRESH. CKE is an SSTL_2 input but
will detect an LVCMOS LOW level after VDD is applied.
Input
Chip Selects: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of the
command code.
Input Bank Address: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Input
Address Inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory
array in the respective device bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE
applies to one device bank (A10 LOW, device bank selected by
BA0, BA1) or all device banks (A10 HIGH). The address inputs
also provide the op-code during a MODE REGISTER SET
command. BA0 and BA1 define which mode register (mode
register or extended mode register) is loaded during the LOAD
MODE REGISTER command.
Input Data Write Mask: DM LOW allows WRITE operation. DM HIGH
blocks WRITE operation. DM state does not affect READ
command.
Input/ Data Strobe: Output with READ data, input with WRITE data.
Output DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.
Input/ Check Bits.
Output
PDF: 09005aef81c73825/Source: 09005aef81c73837
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, 2004, 2005 Micron Technology, Inc. All rights reserved.

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MT18VDVF6472D

512MB DDR SDRAM VLP Registered DIMM

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