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MT36LSDT12872 데이터시트 PDF




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부품번호 MT36LSDT12872 기능
기능 1GB Synchronous DRAM Module
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MT36LSDT12872 데이터시트, 핀배열, 회로
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Features
Synchronous DRAM Module
MT36LSDT12872 – 1GB
MT36LSDT25672 – 2GB
For the latest data sheet, refer to Micron’s Web site: www.micron.com/products/modules
Features
• 168-pin, dual in-line memory module (DIMM)
• PC100- and PC133-compliant
• Registered inputs with one-clock delay
• Phase-lock loop (PLL) clock driver to reduce loading
• Utilizes 125 MHz and 133 MHz SDRAM
components
• Supports ECC error detection and correction
• 1GB (128 Meg x 72) and 2GB (256 Meg x 72)
• Single +3.3V power supply
• Fully synchronous; all signals registered on positive
edge of PLL clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal SDRAM banks for hiding row access/
precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge
• Auto refresh mode
• Self refresh mode: 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Serial presence-detect (SPD)
• Gold edge contacts
Table 1:
Timing Parameters
CL = CAS (READ) latency
Module
Marking
-13E
-133
Clock
133 MHz
133 MHz
Access Time
CL = 2
5.4ns
CL = 3
5.4ns
Setup
Time
1.5
1.5
Hold
Time
0.8
0.8
Figure 1: 168-Pin DIMM (MO-161)
Standard 1.70in. (43.18mm)
Low-Profile 1.20in. (30.48mm)
Options
• Package
168-pin DIMM (standard)
168-pin DIMM (lead-free)
• Frequency/CAS Latency2
133 MHz/CL = 2
133 MHz/CL = 3
• PCB
Standard 1.70in (43.18mm)
Low-Profile 1.20in. (30.48mm)
Marking
G
Y1
-13E
-133
See note on page 2
See note on page 2
Notes: 1. Contact Micron for product availability.
2. Registered mode adds one clock cycle to CL.
Table 2: Address Table
Parameter
Refresh Count
Device Banks
Device Configuration
Row Addressing
Column Addressing
Module Ranks
1GB
8K
4 (BA0, BA1)
256Mb (64 Meg x 4)
8K (A0–A12)
2K (A0–A9, A11)
2 (S0#, S2#; S1#, S3#)
2GB
8K
4 (BA0, BA1)
512Mb (128 Meg x 4)
8K (A0–A12)
4K (A0–A9, A11, A12)
2 (S0#, S2#; S1#, S3#)
PDF: 09005aef80b1835d/Source: 09005aef80b18348
SD36C128_256x72G.fm - Rev. E 6/05 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.




MT36LSDT12872 pdf, 반도체, 판매, 대치품
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Pin Assignments and Descriptions
Table 5:
Pin Descriptions
Pin numbers may not correlate with symbol order; refer to Table 4 on page 3 for more information
Pin Numbers
Symbol
Type
Description
27, 111, 115
42, 79, 125, 163
128
30, 45, 114, 129
28, 29, 46, 47, 112, 113, 130,
131
39, 122
33–38, 117–121, 123, 126
83
165–167
147
2–5, 7–11, 13–17, 19–20,
55–58, 60, 65–67, 69–72,
74–77, 86–89, 91–95, 97–101,
103–104, 139–142, 144,
149–151, 153–156, 158–161
21, 22, 52, 53, 105, 106, 136,
137
82
RAS#, CAS#, WE#
CK0–CK3
CKE0
S0#–S3#
DQMB0–DQMB7
BA0, BA1
A0–A12
SCL
SA0–SA2
REGE
DQ0–DQ63
CB0–CB7
SDA
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input/
Output
Input/
Output
Input/
Output
Command inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Clock: CK0 is distributed through an on-board PLL to all
devices. CK1–CK3 are terminated.
Clock enable: CKE activates (HIGH) and deactivates (LOW) the
CK0 signal. Deactivating the clock provides POWER-DOWN
and SELF REFRESH operation (all device banks idle) or CLOCK
SUSPEND operation (burst access in progress). CKE is
synchronous except after the device enters power-down and
self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CK,
are disabled during power-down and self refresh modes,
providing low standby power.
Chip select: S# enable (registered LOW) and disable (registered
HIGH) the command decoder. All commands are masked when
S# are registered HIGH. S# are considered part of the
command code.
Input/Output mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-
clock latency) when DQMB is sampled HIGH during a READ
cycle.
Bank address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address inputs: Provide the row address for ACTIVE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command.
Serial clock for presence-detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Presence-Detect address inputs: These pins are used to
configure the presence-detect device.
Register enable: REGE permits the DIMM to operate in
“buffered” mode (LOW) or “registered” mode (HIGH).
Data I/Os: Data bus.
Check bits.
Serial presence-detect data: SDA is a bidirectional pin used to
transfer addresses and data into and data out of the presence-
detect portion of the module.
PDF: 09005aef80b1835d/Source: 09005aef80b18348
SD36C128_256x72G.fm - Rev. E 6/05 EN
4 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.

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MT36LSDT12872 전자부품, 판매, 대치품
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
General Description
General Description
The MT36LSDT12872 and MT36LSDT25672 are high-speed CMOS, dynamic random-
access, 1GB and 2GB memory modules organized in x72 (ECC) configurations. SDRAM
modules use internally configured quad-bank SDRAM devices with a synchronous inter-
face (all signals are registered on the positive edge of clock signal CK).
Read and write accesses to SDRAM modules are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1
select the device bank; A0–A12, select the device row). The address bits registered coinci-
dent with the READ or WRITE command are used to select the starting column location
for the burst access.
SDRAM modules provide for programmable read or write burst lengths of 1, 2, 4, or 8
locations, or full page, with a burst terminate option. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
sequence.
SDRAM modules use an internal pipelined architecture to achieve high-speed opera-
tion. Precharging one device bank while accessing one of the other three device banks
will hide the PRECHARGE cycles and provide seamless, high-speed, random-access
operation.
SDRAM modules are designed to operate in 3.3V, low-power memory systems. An auto
refresh mode is provided, along with a power-saving, power-down mode. All inputs and
outputs are LVTTL-compatible.
SDRAM modules offer substantial advances in DRAM operating performance, including
the ability to synchronously burst data at a high data rate with automatic column-
address generation, the ability to interleave between device banks in order to hide pre-
charge time, and the capability to randomly change column addresses on each clock
cycle during a burst access. For more information regarding SDRAM operation, refer to
the 256Mb or 512Mb SDRAM component data sheets.
PLL and Register Operation
These modules can be operated in either registered mode (REGE pin HIGH), where the
control/address input signals are latched in the register on one rising clock edge and
sent to the SDRAM devices on the following rising clock edge (data access is delayed by
one clock), or in buffered mode (REGE pin LOW) where the input signals pass through
the register/buffer to the SDRAM devices on the same clock.
A phase-lock loop (PLL) on the modules is used to redrive the clock to the SDRAM
devices to minimize system clock loading. (CK0 is connected to the PLL, and CK1, CK2,
and CK3 are terminated.)
Serial Presence-Detect Operation
These modules incorporate serial presence-detect (SPD). The SPD function is imple-
mented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes.
The first 128 bytes can be programmed by Micron to identify the module type and vari-
ous SDRAM organizations and timing parameters. The remaining 128 bytes of storage
are available for use by the customer. System READ/WRITE operations between the
master (system logic) and the slave EEPROM device (DIMM) occur via a standard I2C
bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which
provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on
the module, permanently disabling hardware write protect.
PDF: 09005aef80b1835d/Source: 09005aef80b18348
SD36C128_256x72G.fm - Rev. E 6/05 EN
7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.

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부품번호상세설명 및 기능제조사
MT36LSDT12872

1GB Synchronous DRAM Module

Micron
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