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MT4LSDT464A 데이터시트 PDF




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기능 32MB SDRAM Unbuffered DIMM
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MT4LSDT464A 데이터시트, 핀배열, 회로
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Features
SDRAM Unbuffered DIMM (UDIMM)
MT4LSDT464A – 32MB
MT4LSDT864A(I) – 64MB
MT4LSDT1664A(I) – 128MB
For component data sheets, refer to Micron’s Web site: www.micron.com
Features
• 168-pin, dual in-line memory module (DIMM)
• PC100- and PC133-compliant
• Unbuffered
• 32MB (4 Meg x 64)2, 64MB (8 Meg x 64),
128MB (16 Meg x 64)
• Single +3.3V power supply
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal SDRAM banks for hiding row access/
precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes CONCURRENT AUTO
PRECHARGE and auto refresh modes
• Self refresh mode: 64ms, 4,096-cycle refresh
for 32MB and 64MB; 64ms, 8,192-cycle refresh
for 128MB
• LVTTL-compatible inputs and outputs
• Serial presence-detect (SPD)
• Gold edge contacts
Figure 1: 168-Pin DIMM (MO-161)
Standard 25.4mm (1.0in)
Options
• Package
– 168-pin DIMM (standard)
– 168-pin DIMM (Pb-free)
• Operating temperature range
– Commercial (0°C to +65°C)
– Industrial (–40°C to +85°C)1, 3
• Frequency/CAS Latency
– 7.5ns (133 MHz)/CL = 2
– 7.5ns (133 MHz)/CL = 3
– 8ns (100 MHz)/CL = 22
• PCB
– Standard 25.40mm (1.0in)
Marking
G
Y
None
I
-13E
-133
-10E
Notes: 1. Contact Micron for product availability.
2. Not recommended for new designs.
3. Industrial temperature option available in
-133 MHz only.
Table 1:
Key Timing Parameters
CL = CAS (READ) latency
Speed Grade
-13E
-133
-10E2
Industry
Nomenclature
PC133
PC133
PC100
Access Time
CL = 2
5.4ns
9ns
CL = 3
5.4ns
7.5ns
Setup Time
-13E
-133
-10E
Hold Time
133 MHz
133 MHz
100 MHz
PDF: 09005aef8078bc7c/Source: 09005aef8078bcd3
SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.




MT4LSDT464A pdf, 반도체, 판매, 대치품
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
Pin Assignments and Descriptions
Table 5:
Pin Descriptions
Pins may not correlate with symbols; refer to Table 4 on page 3 for more information
Pin Numbers
27, 111, 115
42, 79
Symbol
RAS#, CAS#,
WE#
CK0, CK2
128 CKE0
30, 45
S0#, S2#
28, 29, 46, 47, 112, 113,
130, 131
DQMB0–
DQMB7
39, 122
BA0, BA1
33–38, 117–121, 123,
126 (128MB)
A0–A11
(32MB, 64MB)
A0–A12
(128MB)
83
165–167
82
SCL
SA0–SA2
SDA
2–5, 7–11, 13–17, 19–20,
55–58, 60, 65–67, 69–72,
74–77, 86–89, 91–95,
97–101, 103–104, 139–
142, 144, 149–151, 153–
156, 158–161
DQ0–DQ63
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input/Output
Input/Output
Description
Command inputs: RAS#, CAS#, and WE# (along with S#)
define the command being entered.
Clock: CK is driven by the system clock. All SDRAM input
signals are sampled on the positive edge of CK. CK also
increments the internal burst counter and controls the output
registers.
Clock enable: CKE activates (HIGH) and deactivates (LOW)
the CK signal. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all device banks
idle) or CLOCK SUSPEND OPERATION (burst access in progress).
CKE is synchronous except after the device enters power-down
and self refresh modes, where CKE becomes asynchronous
until after exiting the same mode. The input buffers, including
CK, are disabled during power-down and self refresh modes,
providing low standby power.
Chip select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
Input/output mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-
clock latency) when DQMB is sampled HIGH during a READ
cycle.
Bank address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address inputs: Provide the row address for ACTIVE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command.
Serial clock for presence-detect: SCL is used to synchronize
the presence-detect data transfer to and from the module.
Presence-detect address inputs: These pins are used to
configure the presence-detect device.
Serial presence-detect data: SDA is a bidirectional pin used
to transfer addresses and data into and out of the presence-
detect portion of the module.
Data I/Os: Data bus.
PDF: 09005aef8078bc7c/Source: 09005aef8078bcd3
SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
4 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.

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MT4LSDT464A 전자부품, 판매, 대치품
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
General Description
General Description
The Micron MT4LSDT464A, MT4LSDT864A(I), and MT4LSDT1664A(I) are high-speed
CMOS, dynamic random access, 32MB, 64MB, and 128MB memory modules organized
in a x64 configuration. These modules use SDRAM devices which are internally config-
ured as quad-bank DRAMs with a synchronous interface (all signals are registered on the
positive edge of the clock signals CK).
Read and write accesses to the SDRAM module are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1
select the device bank, A0–A11 for 32MB and 64MB; A0–A12 for 128MB select the device
row). The address bits registered coincident with the READ or WRITE command (A0–A7
for 32MB; A0–A8 for 64MB and 128MB) are used to select the starting device column
location for the burst access.
These modules provide for programmable READ or WRITE burst lengths of 1, 2, 4, or 8
locations, or the full page with a burst terminate option. An auto precharge function
may be enabled to provide a self-timed row precharge that is initiated at the end of the
burst sequence. These modules use an internal pipelined architecture to achieve high-
speed operation. This architecture is compatible with the 2n rule of prefetch architec-
tures, but it also allows the column address to be changed on every clock cycle to achieve
a high-speed, fully random access. Precharging one device bank while accessing one of
the other three device banks will hide the PRECHARGE cycles and provide seamless,
high-speed, random access operation.
These modules are designed to operate in 3.3V, low-power memory systems. An auto
refresh mode is provided, along with a power-saving, power-down mode. All inputs,
outputs, and clocks are LVTTL-compatible.
SDRAM modules offer substantial advances in DRAM operating performance, including
the ability to synchronously burst data at a high data rate with automatic column-
address generation, the ability to interleave between internal banks in order to hide
precharge time, and the capability to randomly change column addresses on each clock
cycle during a burst access. For more information regarding SDRAM operation, refer to
the 64Mb, 128Mb, or 256Mb SDRAM component data sheets.
Serial Presence-Detect Operation
These modules incorporate serial presence-detect (SPD). The SPD function is imple-
mented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes.
The first 128 bytes can be programmed by Micron to identify the module type and
various SDRAM organizations and timing parameters. The remaining 128 bytes of
storage are available for use by the customer. System READ/WRITE operations between
the master (system logic) and the slave EEPROM device (DIMM) occur via a standard IIC
bus using the DIMM’s SCL (clock) and SDA (data) signals. Write protect (WP) is tied to
ground on the module, permanently disabling hardware write protect.
Initialization
SDRAMs must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may result in undefined operation. Once power is
applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is
PDF: 09005aef8078bc7c/Source: 09005aef8078bcd3
SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.

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