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MT5VDDT1672H 데이터시트 PDF




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부품번호 MT5VDDT1672H 기능
기능 128MB DDR SDRAM Small-Outline DIMM
제조업체 Micron
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MT5VDDT1672H 데이터시트, 핀배열, 회로
128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM
Features
DDR SDRAM Small-Outline DIMM
MT5VDDT1672H – 128MB
MT5VDDT3272H – 256MB
For component data sheets, refer to Micron’s Web site: www.micron.com
Features
• 200-pin, small-outline dual in-line memory module
(SODIMM)
• Fast data transfer rates: PC-2100, PC-2700,
or PC-3200
• 128MB2 (16 Meg x 72) and 256MB (32 Meg x 72)
• Supports ECC error detection and correction
• VDD = VDDQ = +2.5V
• VDDSPD = +2.3V to +3.6V
• JEDEC-standard 2.5V I/O (SSTL_2-compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data (source-synchronous data
capture)
• Differential clock inputs (CK and CK#)
• Four internal device banks for concurrent operation
• Selectable burst lengths (BL): 2, 4, or 8
• Auto precharge option
• Auto refresh and self refresh modes: 7.8125µs
maximum average periodic refresh interval
• Serial presence-detect (SPD) with EEPROM
• Selectable READ CAS latency for maximum
compatibility
• Gold edge contacts
Figure 1: 200-Pin SODIMM (MO-224 R/C C)
Module height: 31.75mm (1.25in)
Options
Marking
• Operating temperature1
– Commercial (0°C TA +70°C)
– Industrial (–40°C TA +85°C)
• Package
– 200-pin SODIMM (standard)2
None
I
G
– 200-pin SODIMM (Pb-free)
Y
• Memory clock, frequency, CAS latency
– 5ns (200 MHz), 400 MT/s, CL = 3
-40B3
– 6ns (167 MHz), 333 MT/s, CL = 2.5
-335
– 7.5ns (133 MHz), 266 MT/s, CL = 2
-262
– 7.5ns (133 MHz), 266 MT/s, CL = 2
-26A
– 7.5ns (133 MHz), 266 MT/s, CL = 2.5
-265
• PCB height
– 31.75mm (1.25in)
Notes: 1. Contact Micron for industrial temperature
module offerings.
2. Consult factory for product availability.
3. -40B only available for 256MB modules.
Table 1:
Speed
Grade
-40B
-335
-262
-26A
-265
Key Timing Parameters
Industry Nomenclature
PC-3200
PC-2700
PC-2100
PC-2100
PC-2100
Data Rate (MT/s)
CL = 3
400
CL = 2.5
333
333
266
266
266
CL = 2
266
266
266
266
200
tRCD
(ns)
15
15
15
20
20
tRP
(ns)
15
15
15
20
20
tRC
(ns)
55
60
60
65
65
PDF: 09005aef80a8e793/Source: 09005aef80a8e767
dd5c16_32x72h.fm - Rev. F 2/07 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.




MT5VDDT1672H pdf, 반도체, 판매, 대치품
128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM
Pin Assignments and Descriptions
Table 6: Pin Descriptions
Symbol
WE#, CAS#,
RAS#
CK0, CK0#, CK1,
CK1#, CK2, CK2#
Type
Input
Input
CKE0
Input
S0# Input
BA0, BA1
A0–A12
Input
Input
DM0–DM8
SDA
SCL
SA0–SA2
DQS0–DQS8
CB0–CB7
DQ0–DQ63
VREF
VDD
VSS
VDDSPD
NC
Input
Input/
Output
Input
Input
Input/
Output
Input/
Output
Input/
Output
Supply
Supply
Supply
Supply
Description
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command
being entered.
Clocks: CK and CK# are differential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge of CK and negative edge
of CK#. Output data (DQs and DQS) is referenced to the crossings of CK and CK#.
Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock,
input buffers and output drivers.
Chip select: S# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when S# is registered HIGH. S# is
considered part of the command code.
Bank address: BA0 and BA1 define the device bank to which an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied.
Address inputs: Provide the row address for ACTIVE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective device bank. A10 sampled
during a PRECHARGE command determines whether the PRECHARGE applies to
one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks
(A10 HIGH). The address inputs also provide the op-code during a MODE
REGISTER SET command. BA0 and BA1 define which mode register (mode register
or extended mode register) is loaded during the LOAD MODE REGISTER
command.
Data mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with that input data during a WRITE access. DM
is sampled on both edges of DQS. Although DM pins are input-only, the DM
loading is designed to match that of DQ and DQS pins.
Serial presence-detect data: SDA is a bidirectional pin used to transfer
addresses and data into and out of the presence-detect portion of the module.
Serial clock for presence-detect: SCL is used to synchronize the presence-
detect data transfer to and from the module.
Presence-detect address inputs: These pins are used to configure the
presence-detect device.
Data strobe: Output with READ data, input with WRITE data. DQS is edge-
aligned with READ data, centered in WRITE data. Used to capture data.
Check bits.
Data input/output: Data bus.
SSTL_2 reference voltage.
Power supply: +2.5V ±0.2V. (-40B speed grade requires 2.6V ±0.1V)
Ground.
Serial EEPROM positive power supply: +2.3V to +3.6V.
No connect: These pins should be left unconnected.
PDF: 09005aef80a8e793/Source: 09005aef80a8e767
dd5c16_32x72h.fm - Rev. F 2/07 EN
4 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.

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MT5VDDT1672H 전자부품, 판매, 대치품
128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed in Table 7 may cause permanent damage to the
module. This is a stress rating only, and functional operation of the module at these or
any other conditions above those indicated in each device’s data sheet is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
Table 7: Absolute Maximum Ratings
Symbol
VDD
VREF
VTT
VIH(DC)
VIL(DC)
II
IOZ
IOH
IOL
IOH
IOL
TA
Parameter/Condition
VDD supply voltage relative to VSS
I/O reference voltage
I/O termination voltage (system)
Input high (logic 1) voltage
Input low (logic 0) voltage
Input leakage current; Any input
0V VIN VDD; VREF pin 0V VIN 1.35V
(All other pins not under test = 0V)
Command/address,
RAS#, CAS#, WE#,
CKE, S#, BA
CK0, CK0#,
CK1, CK1#
DM, CK2, CK2#
Output leakage current
(DQ pins are disabled; 0V VOUT VDDQ)
DQ, DQS
Output levels
High current (VOUT = VDDQ - 0.373V, MIN VREF, MIN VTT)
Low current (VOUT = 0.373V, MAX VREF, MAX VTT)
Output levels (reduced drive option)
High current (VOUT = VDDQ - 0.373V, MIN VREF, MIN VTT)
Low current (VOUT = 0.373V, MAX VREF, MAX VTT)
Module ambient operating temperature
Commercial
Industrial
Min
2.3
0.49 × VDDQ
VREF - 0.04
VREF + 0.15
–0.3
–10
Max
2.7
0.51 × VDDQ
VREF + 0.04
VDD + 0.3
VREF - 0.15
10
Units
V
V
V
V
V
µA
–4
–2
–5
–16.8
16.8
–9
9
0
–40
4
2
5 µA
– mA
– mA
– mA
– mA
+70 °C
+85
Input Capacitance
Micron encourages designers to simulate the performance of the module to achieve
optimum values. Simulations are significantly more accurate and realistic than a gross
estimation of module capacitance when inductance and delay parameters associated
with trace lengths are used in simulations. JEDEC modules are currently designed using
simulations to close timing budgets.
PDF: 09005aef80a8e793/Source: 09005aef80a8e767
dd5c16_32x72h.fm - Rev. F 2/07 EN
7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.

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