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기능 1GB DDR2 SDRAM VLP Mini-RDIMM
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MT9HVF12872PK 데이터시트, 핀배열, 회로
512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM
Features
DDR2 SDRAM VLP Mini-RDIMM
MT9HVF6472(P)K – 512MB
MT9HVF12872(P)K – 1GB
For component data sheets, refer to Micron’s Web site: www.micron.com
Features
• 244-pin, very low profile mini registered dual in-line
memory module (VLP Mini-RDIMM)
• Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300, or PC2-6400
• 512MB (64 Meg x 72) or 1GB (128 Meg x 72)
• Supports ECC error detection and correction
• VDD = VDDQ = +1.8V
• VDDSPD = +1.7V to +3.6V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4n-bit prefetch architecture
• Multiple internal device banks for concurrent
operation
• Supports duplicate output strobe (RDQS/RDQS#)
• Programmable CAS# latency (CL)
• Posted CAS# additive latency (AL)
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts
• Single rank
Figure 1: 244-Pin VLP Mini-RDIMM
PCB height: 18.2mm (0.72in)
Options
• Parity
• Operating temperature1
Commercial (0°C TA +70°C)
Industrial (–40°C TA +85°C)
• Package
244-pin DIMM (Pb-free)
• Frequency/CAS latency2
2.5ns @ CL = 5 (DDR2-800)
2.5ns @ CL = 6 (DDR2-800)
3ns @ CL = 5 (DDR2-667)
3.75ns @ CL = 4 (DDR2-533)
5.0ns @ CL = 3 (DDR2-400)
• PCB height
18.2mm (0.72in)
Marking
P
None
I
Y
-80E
-800
-667
-53E
-40E
Notes: 1. Contact Micron for industrial temperature
module offerings.
2. CL = CAS (READ) latency; registered mode
will add one clock cycle to CL.
Table 1:
Speed
Grade
-80E
-800
-667
-53E
-40E
Key Timing Parameters
Industry
Nomenclature
PC2-6400
PC2-6400
PC2-5300
PC2-4200
PC2-3200
CL = 6
800
Data Rate (MT/s)
CL = 5
800
667
667
CL = 4
533
53E
533
533
400
CL = 3
400
400
400
tRCD
(ns)
12.5
15
15
15
15
tRP
(ns)
tRC
(ns)
12.5 55
15 55
15 55
15 55
15 55
PDF: 09005aef81c9620b/Source: 09005aef81c961ec
HVF9C64_128x72K.fm - Rev. C 3/07 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.




MT9HVF12872PK pdf, 반도체, 판매, 대치품
512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM
Pin Assignments and Descriptions
Table 6: Pin Descriptions
Symbol
Type
Description
ODT0
Input
(SSTL_18)
On-die termination: ODT (registered HIGH) enables termination resistance internal to
the DDR2 SDRAM. When enabled, ODT is only applied to each of the following pins: DQ,
DQS, DQS#, RDQS, RDQS#, CB, and DM. The ODT input will be ignored if disabled via the
LOAD MODE (LM) command.
CK0, CK0#
Input Clock: CK and CK# are differential clock inputs. All address and control input signals are
(SSTL_18) sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data
(DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.
CKE0
Input Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates
(SSTL_18) clocking circuitry on the DDR2 SDRAM.
S0# Input Chip select: S# enables (registered LOW) and disables (registered HIGH) the command
(SSTL_18) decoder. All commands are masked when S# is registered HIGH. S# provides for external
rank selection on systems with multiple ranks. S# is considered part of the command code.
RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
(SSTL_18) entered.
BA0, BA1
(512MB)
BA0–BA2
(1GB)
Input Bank address inputs: BA0–BA1/BA2 define to which device bank an ACTIVE, READ,
(SSTL_18) WRITE, or PRECHARGE command is being applied. BA0–BA1/BA2 define which mode
register, including MR, EMR, EMR(2), and EMR(3), is loaded during the LM command.
A0–A13
Input
(SSTL_18)
Address inputs: Provide the row address for ACTIVE commands, and the column address
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0–BA1/BA2) or all device banks (A10 HIGH). The address inputs also provide
the op-code during a LM command.
PAR_IN
Input Parity bit for the address and control bus.
(SSTL_18)
SCL Input Serial clock for presence-detect: SCL is used to synchronize the presence-detect data
(SSTL_18) transfer to and from the module.
SA0–SA2
Input Presence-detect address inputs: These pins are used to configure the presence-detect
(SSTL_18) device.
RESET#
Input Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal can be
(SSTL_18) used during power-up to ensure that CKE is LOW and DQs are High-Z.
DQ0–DQ63
I/O Data input/output: Bidirectional data bus.
(SSTL_18)
DQS0–DQS8,
DQS0#–DQS8#
I/O
(SSTL_18)
Data strobe: Output with read data, input with write data for source synchronous
operation. Edge-aligned with read data, center-aligned with write data. DQS# is only used
when differential data strobe mode is enabled via the LM command. DQS9#–DQS17# are
only used when RDQS# is enabled via the LM command.
DM0–DM8
(RDQS0–RDQS8)
I/O
(SSTL_18)
Input data mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on
both edges of DQS. Although DM pins are input-only, the DM loading is designed to match
that of DQ and DQS pins. If RDQS is enabled, DQS0#–DQS8# are used only during the READ
command. If RDQS is disabled, RDQS0–RDQS8 become DM0–DM8 and RDQS0#–RDQS8# are
not used.
CB0–CB7
I/O Check bits.
(SSTL_18)
SDA I/O Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and
(SSTL_18) data into and out of the presence-detect portion of the module.
ERR_OUT
Output Parity error found on the address and control bus.
(open drain)
VDD/VDDQ
Supply Power supply: 1.8V ±0.1V.
PDF: 09005aef81c9620b/Source: 09005aef81c961ec
HVF9C64_128x72K.fm - Rev. C 3/07 EN
4 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.

4페이지










MT9HVF12872PK 전자부품, 판매, 대치품
512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM
General Description
General Description
The MT9HVF6472(P)K and MT9HVF12872(P)K DDR2 SDRAM modules are high-speed,
CMOS, dynamic random-access 512MB and 1GB memory modules organized in a
x72 configuration. DDR2 SDRAM modules use internally configured 4-bank (512Mb) or
8-bank (1Gb) DDR2 SDRAM devices.
DDR2 SDRAM modules use double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 4n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the DDR2 SDRAM module effectively consists of a single
4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corre-
sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM
device during READs and by the memory controller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data for WRITEs.
DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands are registered at every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of DQS, as well as to both
edges of CK.
Register and PLL Operation
DDR2 SDRAM modules operate in registered mode, where the command/address input
signals are latched in the registers on the rising clock edge and sent to the DDR2 SDRAM
devices on the following rising clock edge (data access is delayed by one clock cycle). A
phase-lock loop (PLL) on the module receives and re-drives the differential clock signals
(CK, CK#) to the DDR2 SDRAM devices. The register(s) and PLL reduce address,
command, control, and clock signal loading by isolating DRAM from the system
controller. PLL clock timing is defined by JEDEC specifications and ensured by use of the
JEDEC clock reference board. Registered mode will add one clock cycle to CL.
Serial Presence-Detect Operation
DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is
implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains
256 bytes. The first 128 bytes are programmed by Micron to identify the module type and
various SDRAM organizations and timing parameters. The remaining 128 bytes of
storage are available for use by the customer. System READ/WRITE operations between
the master (system logic) and the slave EEPROM device occur via a standard I2C bus
using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which
provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to VSS on the
module, permanently disabling hardware write protect.
PDF: 09005aef81c9620b/Source: 09005aef81c961ec
HVF9C64_128x72K.fm - Rev. C 3/07 EN
7 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.

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MT9HVF12872PK

1GB DDR2 SDRAM VLP Mini-RDIMM

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