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Número de pieza | F1E200 | |
Descripción | Cost-Efficient E-Reader Processor up to 720P | |
Fabricantes | Allwinner | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de F1E200 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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F1E200
Cost-Efficient E-Reader Processor up to 720P
Datasheet
Highlights
Optimized ARM926-EJS 16KB
I-Cache/16KB D-Cache
16 bits low cost SDR/DDR-I
Support SLC/MLC NAND flash up to
64bits ECC
Support SPI NOR flash
H.264/MPEG1&2/MPEG4/Xvid
decoding up to 1280*720 @ 30fps
Built in USB 2.0 HOST/OTG
Built in MMC/SD/TF Card
Built in Touch Panel Interface
Built in LCD controller with PWM
On-chip Sigma-Delta A/D with SNR up
to 95dB(A-Weight)
On-chip Sigma-Delta D/A and PA with
SNR up to 100dB(A-Weight)
Fully support PMU application
Package - eLQFP128 (16mm*16mm)
USB HOST/OTG
MIC/Headphone
OSD/TCON
CVBS
KEY
USB OTG Audio Codec
ARM926-
EJS
DE/TCON
Video
Encoder
LRADC
Video
Decoder
JPEG
Decoder
AHB/APB Bus
Touch Panel
TP
DMA
Timer
DMA
DDR
PLL
UART
TWI
IR
IRRX
SD/MMC
SD/MMC
PIO
PWM
Crystal
PIO PWM
1 page 7.9.1 USB Overview.............................................................................................................. - 21 -
7.10 TWO WIRE INTERFACE........................................................................................................- 23 -
7.10.1 TWI Controller Description...................................................................................... - 23 -
7.10.2 TWI Controller Timing Diagram.............................................................................. - 23 -
7.11 SPI INTERFACE ...................................................................................................................- 24 -
7.11.1 SPI Description......................................................................................................... - 24 -
7.11.2 SPI Timing Diagram................................................................................................. - 24 -
7.12 UART INTERFACE ..............................................................................................................- 26 -
7.12.1 UART Overview....................................................................................................... - 26 -
7.12.2 UART Timing Diagram ............................................................................................ - 27 -
7.13 IR INTERFACE .....................................................................................................................- 27 -
7.13.1 IR Overview ............................................................................................................. - 27 -
7.13.2 IR Timing Diagram................................................................................................... - 29 -
7.14 AUDIO CODEC ....................................................................................................................- 30 -
7.14.1 Description ............................................................................................................... - 30 -
7.14.2 Feature ...................................................................................................................... - 30 -
7.14.3 Audio Codec Block Diagram ................................................................................... - 30 -
7.15 LRADC..............................................................................................................................- 31 -
7.15.1 Description ............................................................................................................... - 31 -
7.15.2 Feature ...................................................................................................................... - 31 -
7.16 TOUCH PANEL.....................................................................................................................- 31 -
7.16.1 Description ............................................................................................................... - 31 -
7.17 GPIO INTERFACE................................................................................................................- 32 -
7.17.1 Port Description........................................................................................................ - 32 -
7.17.2 Port Configuration Table .......................................................................................... - 32 -
7.18 TV ENCODER......................................................................................................................- 34 -
7.18.1 Feature ...................................................................................................................... - 34 -
7.18.2 Block diagram .......................................................................................................... - 35 -
7.19 UNIVERSAL LCD/TV TIMING CONTROLLER.......................................................................- 35 -
7.19.1 Feature ...................................................................................................................... - 35 -
7.20 VIDEO DECODER ENGINE ...................................................................................................- 35 -
7.20.1 Video Decoder Engine Overview ............................................................................. - 35 -
8 PACKAGE SPECIFICATIONS............................................................................................. - 37 -
This document is supposed to be confidential. Neither institution nor individual is allowed to copy,
print or transfer to third party without authorization from AW; All Rights reserved.
5 Page 33
LD 20
I/O
LCD Data Bus Bit 20
34
LD 21
I/O
LCD Data Bus Bit 21
35
LD 22
I/O
LCD Data Bus Bit 22
36
LD 23
I/O
LCD Data Bus Bit 23
40
LCLK
I/O pull-up
LCD Clock
37
LDE
I/O pull-down
LCD Data Enable
38
LHSYNC I/O pull-down
LCD Horizon Sync
39
LVSYNC I/O pull-down
LCD Vertical Sync
5.4 USB Interface Pin
Pin Num
70
71
69
Pin Name
UDM0
UDP0
UVCC
Type Default Status Description
USB DM signal
USB DP signal
USB 3.3V power
5.5 Touch Panel Interface Pin
Pin Num
60
61
62
63
Pin Name
X1
X2
Y1
Y2
Type Default Status Description
Touch Panel X1 input
Touch Panel X2 input
Touch Panel Y1 input
Touch Panel Y1 input
5.6 Audio Codec Interface Pin
Pin Num
46
50
49
48
47
57
58
52
Pin Name Type Default Status
HPL
HPR
HPCOM
HPCOM-FB
HPVCC
FMINL
FMINR
MICIN
Description
Headphone Left Channel Output
Headphone Right Channel Output
Headphone Common Mode
Headphone Common Mode Feedback
Headphone 3.0V power bypass
Line Input Left Channel
Line Input Right Channel
Microphone Left Channel Input
This document is supposed to be confidential. Neither institution nor individual is allowed to copy,
print or transfer to third party without authorization from AW; All Rights reserved.
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet F1E200.PDF ] |
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