PDF 29XL12DF Data sheet ( Hoja de datos )

Número de pieza	29XL12DF
Descripción	MBM29XL12DF
Fabricantes	Fujitsu
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No Preview Available ! FUJITSU SEMICONDUCTOR DATA SHEET DS05-20901-1E PAGE MODE FLASH MEMORY CMOS 128M (8M × 16/4M × 32) BIT MBM29XL12DF-70/80 s DESCRIPTION The MBM29XL12DF is 128M-bit, 3.0 V-only Page mode and dual operation Flash memory organized as 8M words by 16 bits or 4M words by 32 bits. The device is offered in 90-pin SSOP and 96-ball FBGA packages. This device is designed to be programmed in-system with the standard system 3.0 V Vcc supply. 12.0 V Vpp and 5.0 V Vcc are not required for program or erase operations. The device can also be reprogrammed in standard EPROM programmers. s PRODUCT LINEUP (Continued) Part No. Ordering Part Number Suffix VCC (V) Max Random Address Access Time (ns) Max Page Address Access Time (ns) Max CE Access Time (ns) Max OE Access Time (ns) 70 3.0 to 3.6 70 25 70 25 MBM29XL12DF 80 2.7 to 3.1 80 30 80 30 s PACKAGES 90-pin plastic SSOP 96-ball plastic FBGA (FPT-90P-M01) (BGA-96P-M02) 1 page MBM29XL12DF-70/80 s PIN ASSIGNMENTS N.C. N.C. N.C. RESET RY/BY A0 A1 A2 A3 A4 A5 VCC DQ0 DQ16 DQ1 DQ17 Vss VCC DQ2 DQ18 DQ3 DQ19 DQ4 DQ20 DQ5 DQ21 Vss VCC DQ6 DQ22 DQ7 DQ23 Vss A6 A7 A8 A9 A10 A11 A12 N.C. N.C. N.C. N.C. N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 SSOP (TOP VIEW) (FPT-90P-M01) 90 N.C. 89 N.C. 88 ACC 87 WP 86 WE 85 N.C. 84 A21 83 A20 82 DW/W 81 OE 80 CE 79 Vss 78 DQ31/A-1 77 DQ15 76 DQ30 75 DQ14 74 Vss 73 VCC 72 DQ29 71 DQ13 70 DQ28 69 DQ12 68 DQ27 67 DQ11 66 DQ26 65 DQ10 64 Vss 63 VCC 62 DQ25 61 DQ9 60 DQ24 59 DQ8 58 VCC 57 A19 56 A18 55 A17 54 A16 53 A15 52 A14 51 A13 50 N.C. 49 N.C. 48 N.C. 47 N.C. 46 N.C. (Continued) 5 5 Page MBM29XL12DF-70/80 MBM29XL12DF Command Definitions Table Command Sequence Bus Write Cy- First Bus Write Cycle Second Bus Write Cycle Third Bus Write Cycle Fourth Bus Read/Write Cycle Fifth Bus Write Cycle Sixth Bus Write Cycle Seventh Bus Write Cycle cles Req’d Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Read/Reset 1 2 XXXh F0h RA RD — — — — — — — — — — Read/Reset DW 1 W 4 555h 2AAh 555h AAh 55h F0h RA RD — AAAh 555h AAAh — — — — — Autoselect DW 3 555h AAh 2AAh 55h (BA) 555h 90h — — — — — — — — W AAAh 555h AAAh Program DW 555h 2AAh 555h 4 AAh 55h A0h PA PD — — — — — — W AAAh 555h AAAh DW 555h 2AAh 555h 555h 2AAh 555h Chip Erase 6 AAh 55h 80h AAh 55h 10h — W AAAh 555h AAAh AAAh 555h AAAh — DW 555h 2AAh 555h 555h 2AAh Sector Erase 6 AAh 55h 80h AAh 55h SA 30h — W AAAh 555h AAAh AAAh 555h — Program/Erase Suspend 1 BA B0h — — — — — — — — — — — — Program/Erase Resume 1 BA 30h — — — — — — — — — — — — Set to Fast Mode DW W 3 555h 2AAh 555h AAh 55h 20h AAAh 555h AAAh — — — — — — — — Fast Program 2 DW W 2 XXXh A0h PA XXXh PD — — — — — — — — — — Reset from DW Fast Mode 2 W 2 BA BA 90h XXXh XXXh F0h 6 — — — — — — — — — — Extended DW Sector Group 4 XXXh 60h SGA 60h SGA 40h SGA SD — — — — — — Protection3 W Query 4 DW (BA) 55h 1 98h — — — — — — — — — — — — W (BA) 55h HiddenROM DW Entry W 3 555h 2AAh 555h AAh 55h 88h AAAh 555h AAAh — — — — — — — — HiddenROM DW Program 5 W 4 555h 2AAh AAh AAAh 555h 55h 555h AAAh A0h (HRA) PA PD — — — — — — HiddenROM DW Exit *5 W 4 555h 2AAh 555h AAh 55h 90h XXXh 00h — AAAh 555h AAAh — — — — — (Continued) 11 11 Page

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