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6501 데이터시트, 핀배열, 회로
, . .commodore
~ aarnlconduCl:ar group
~UYAJ@~
MPS
6500/1
ONE-CHIP
MICROCOMPUTER
8500/1 ONE-CHIP MICROCOMPUTER
INTRODucnoN
The MOS Technology 6500/1 Is a complete, high-performance 8-blt NMOS microcomputer on a single chip, and
Is totally upward/downward software compatible with all members of the 6500 family.
The 650011 consists of a 6502 CPU, an Internal clock oscillator, 2048 bytes of Read Only Memory (ROM), 64 bytes
of Random Access Memory (RAM) and flexible Interface circuitry. The· interface circuitry includes a 18-blt
programmable counter/latch with four operating modes, 32 bidirectional Input/output lines (Including two edge-
sensitive lines), five Interrupts and a counter I/O line.
PRODUCT SUPPORT
To allow prototype clrCl~lt development, Mos Tech-
nology offers a PROM compatible 64-pln Emulator de-
vice. This device provides all 650011 Interface lines
plus routing the address bus, data bus, and asso-
ciated control lines off the chip to be connected to
external memory.
Order
Number
ORDERING INFORMATION
Package Frequency Temperature
Type Option
Range
MPS65OOI1
Plastic 1 MHz
MCS6500/1 Ceramic 1 MHz
MPS65OOI1A Plastic 2 MHz
MCS65OOI1A Ceramic 2 MHz
MCS65OOI1E Emulator Device 1MHz
'MCS65OOI1EA Emulator Device 2MHz
O°C to 70°C
O°C to 70°C
O°C to 70°C
O°C to 70°C
Note: The RC frequency option is available only in the
1 MHz 6500/1.
XTU
)(flO
RES
Rgj
vee
vss
VRR
¢a;> PAO-PA7
¢a~ P8(H2B7
¢a ~ pc()'PC7
¢a::> POOPD7
CNTR
FEATURES
• 6502 CPU
-Software upward/downward compatibility
-Decimal or binary arithmetic modes
-13 addressing modes
-True direct and indirect indexing
-Memory addressable 110
• 2048 x 8 mask programmable ROM
• 64 x 8 static RAM
• 32 bi<iirectional TIL compatible 110 lines (4 ports)
• 1 bi<iirectional TIL compatible counter I/O line
• 16-bit programmable counter/latch with four
modes
-Interval Timer -Event Counter
-Pulse Generator -Pulse Width Measurement
• Five Interrupts
-Reset
-Non·maskable
-Two external edge sensitive
-Counter
• 1 of 3 frequency references
-Crystal -Clock -RC (resistor only)
• 4 MHz max crystal or clock external frequency
• 2 MHz or 1 MHz internal clock
• 1 /Ls minimum instruction execution
• N-channel, silicon gate, depletion load technology
• Single + 5V power supply
• 500 mW operating power
• Separate power pin for RAM
• 40 pin DIP
• 64 pin PROM compatible Emulator device
Interface Diagram
2-2




6501 pdf, 반도체, 판매, 대치품
MPS
6500/1
The Counter Overflow bit Is cleared when the LC is
rElad or Counter preset is performed by writing Into ad-
dress 088.
COUNTER MODES
The Counter operates In any of four modes. These
modes are selected by the Counter Mode Control bits
In the Control Register.
Mode
Interval Timer
Pulse Generator
Event Counter
Pulse Width Measurement
CMC 1
---0-
o
1
1
CMCO
-0-
1
o
1
The Interval Timer, Pulse Generator, and Pulse
Width Measurement Modes are 02 clock counter
modes. The Event Counter Mode counts the occur-
rences of an external event on the CNTR line.
Interval Timer (Mode 0)
In this mode the Counter is free running and decre-
ments at the 02 clock rate. Counter overflow sets the
Control Register status bit and causes the Counter to
be preset to the Latch value.
The CNTR line Is held in the high state.
Pulse Generator (Mode 1)
In this mode the Counter is free running and decre-
ments at the 02 clock rate. Counter overflow sets the
Control Register status bit and causes the Counter to
be preset to the Latch value.
The CNTR line toggles from one state to the other
when Counter overflow occurs. Writing to address 088
will also toggle the CNTR line.
A symmetric or asymmetlc output waveform can
be generated on the CNTR line in this mode. A one-
shot waveform can easily be generated by changing
from Mode 1 to Mode 0 after only one occurrence of
the output toggle condition.
Event Counter (Mode 2)
In this mode the CNTR line is used as an event In-
put line. The Counter decrements each time a rising
edge Is detected on CNTR. The maximum rate at
which this edge can be detected Is one-half the 02
clock rate. Counter overflow sets the Control Register
status bit and causes the Counter to be preset tb the
Latch value.
Pulse Width Measurement (Mode 3)
This mode allows the accurate measurement of the
duration of a low state on the CNTR line. The Counter
decrements at the 02 clock rate as long as the CNTR
line Is held In the low state. The Counter Is stopped
when CNTR Is In the high state. If the CNTR pin Is left
disconnected, this mode may be selected to stop the
Counter since the Internal pull-up device will cause
the CNTR Input to be In the high state.
RESET CONSIDERATIONS
The occurrence of RES gOing from low to high
causes Initialization of various conditions In the
6500/1. All of the 110 ports (PA, PB, PC, and PO) and
CNTR are forced to the high (Logic 1) state. All bits of
the Control Register are reset to Logic 0, causing the
Interval Timer Mode (Mode 0) to be selected and all in-
terrupt enabled bits to be cleared. Neither the Latch
nor the Counter registers are Initialized by RES. The
Interrupt Disable bit In the CPU Processor Status
Register Is set and the program starts execution at
the address contained in the Reset Vector location.
TEST LOGIC
Special test logiC provides a method for thorou.9!!!Y
testing the 6500/1. Applying a + 10V signal to the RES
line places the 6500/1 in the test mode. While In this
mode, all memory fetches are made from Port PC. Ex-
ternal test equipment can use this feature to test In-
ternal CPU logic and 110. A program can be loaded in-
to RAM allowing the contents of the instruction ROM
to be dumped to any port for external verification.
All 6500/1 microcomputers are tested by MOS
Technology using this feature.
MEMORY ADDRESSABLE 1/0
The 110 ports, registers, and commands are treated
as memory and are assigned specific addresses. See
the system memory map for the addresses. This 110
technique allows the full set of CPU instructions to be
used In the generation and sampling of 110 com-
mands and data. When an instruction is executed
with an 110 address and appropriate RNV state, the
corresponding 110 function is performed.
SYSTEM MEMORY MAP
IRQ Vector High
IRQ Vector Low
RES Vector High
RES Vector Low
NMI Vector High
NMI Vector Low
User Program
Unassigned
»Control Register
Unassigned
Clear PA1 Neg Edge Detected
Clear PAO Pos Edge Detected
Upper Latch and Transfer Latch
to Counter
Lower Count
l!!>Per Count
Lower Latch
Upper Latch
PORTO
PORTC
PORTB
PORTA
< Unassigned
User RAM
HEX
FFF
FFE
FFO
FFC
FFB
ROM
FFA
FF9
800
<
08F
08E
08B
(1) 08A
(1) 089
(2) 088
(2) 087
086
085
084
083
082
081
080
InputlOutput
:} RAM
Notel:
(1) I/O command only; I.e., no stored data.
(2) Clears Counter Overflow-Bit 7 in Control Register.
2-5

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6501 전자부품, 판매, 대치품
MPS
6500/1
ADDRESSING MODES
ACCUMULATOR ADDRESSING-This form of ad-
dressing Is represented with a one byte Instruction,
Implying an operation on the accumulator_
IMMEDIATE ADDRESSING-In Immediate ad-
dressing, the operand Is contained In the second byte
of the Instruction, with no further memory addressing
required_
ABSOLUTE ADDRESSING-In absolute address-
Ing, the second byte of the Instruction speCifies the
eight low order bits of the effective address while the
third byte specifies the eight high order bits_
ZERO PAGE ADDRESSING-The zero page In-
structions allow for shorter code and execution times
by only fetching the second byte of the Instruction
and assuming a zero high address byte. Careful use
of the zero page can result In significant Increase In
code efficiency.
INDEXED ZERO PAGE ADDRESSING-(X, Y index-
Ing)-This form of addressing Is used In conjunction
with the Index register and Is referred to as "Zero
Page, X" or "Zero Page, Y." The effective address Is
calculated by adding the second byte to the contents
of the Index register. Since this Is a form of "Zero
Page" addressing, the content of the second byte
references a location In page zero. Additionally due to
the "Zero Page" addressing nature of this mode, no
carry Is added to the high order 8 bits of memory and
crOSSing of page boundaries does not occur.
INDEXED ABSOLUTE ADDRESSING-(X, Y index-
Ing)-This form of addressing Is used In conjunction
with X and Y Index register and Is referred to as "Ab-
solute, X", and "Absolute, Y." The effective address is
formed by adding the contents of X or Y to the ad-
dress contained In the second and third bytes of the
Instruction. This mode allows the Index register to
contain the Index or count value and the Instruction to
contain the base address. This type of indexing
allows any location referencing and the index to
modify multiple fields resulting In reduced coding and
execution time.
IMPLIED ADDRESSING-In the Impll~ address-
Ing mode, the address containing the operand Is Im-
plicitly stated In the operation code of the Instruction.
RELATIVE ADDRESSING-Relative addressing Is
used only with branch Instructions and establishes a
destination for the conditional branch.
The second byte of the Instruction becomes the
operand which Is an "Offset" added to the. contents of
the lower eight bits of the program counter when the
counter Is set at the next Instruction. The range of the
offset Is -128 to + 127 bytes from the next Instruc-
tion.
INDEXED INDIRECT ADDRESSING-In Indexed In-
direct addressing (referred to as [Indirect, X)), the se-
cond byte of the Instruction Is added to the contents
of the X Index register, discarding the carry. The result
of this addition points to a memory location on page
zero whose contents Is the low order eight bits of the
effective address. The next memory location In page
zero contains the high order eight bits of the effective
address. Both memory locations specifying the high
and low order bytes of the effective address. must be
In page zero.
INDIRECT INDEXED ADDRESSING-In indirect
indexed' addreSSing (referred to as [Indirect, Y]),
the second byte of the instruction pOints to a
memory location in page zero. The contents of this
memory location are added to the contents of the
Y index register, the result being the low order
eight bits of the effective address. The carry from
this addition is added to the contents of the next
page zero memory location, the result being the
high order eight bits of the effective address.
ABSOLUTE INDIRECT-The second byte of the
instruction contains the low order eight bits of a
memory location. The high order eight bits of that
memory location are contained in the third byte of
the instruction. The contents of the fully specified
memory location are the low order byte of the
effective address. The next memory location con-
tains the high order byte of the effective address
which Is loaded Into the sixteen bits of the pro-
gram counter.
2-8

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