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6526 데이터시트 PDF




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부품번호 6526 기능
기능 COMPLEX INTERFACE ADAPTER
제조업체 Commodore
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6526 데이터시트, 핀배열, 회로
, . . , commodore
~ aanlcanduct;ar group
~UYAJ@~
MPS
6526
COMPLEX
INTERFACE
ADAPTER
(CIA)
6526 COMPLEX INTERFACE ADAPTER (CIA)
DESCRIPTION
The 6526 Complex Interface Adapter (CIA) is a 65XX bus compatible peripheral Interface device
with extremely flexible timing and I/O capabilities.
FEATURES
• 16 Individually programmable I/O lines
• 8 or 16-Bit handshaking on read or write
• 2 independent, linkable 16-Bit interval timers
• 24-hour (AM/PM) time of day clock with programmable alarm
• 8-Bit shift register for serial I/O
• 2TTL Load capability
• CMOS compatible I/O lines
• 1 or 2 MHz operation available
ORDERING INFORMATION
MXS 6526
1 40 CNT
PAO 2
39 SP
PA1 3
PA2 4
PA3 5
PA4 6
PA5 7
38 RSO
37 RS1
36 RS2
35 RS3
34 RES
PA6 8
33 DBO
PA7 9
32 DB1
PBO 10 6526 31 DB2
PB1 11
30 DB3
PB2 12
29 DB4
PB3 13
28 DB5
PB4 14
27 DB6
PB5 15-
PB6 16
PB7 17
Pc 18
TOO 19
vee 20
26 DB7
25 ~2
24 FLAG
23 es
22 RNV
21 IRQ
2-84




6526 pdf, 반도체, 판매, 대치품
6526 WRITE TIMING DIAGRAM
~2 INPUT
PERIPHERAL
DATA OUT
MPS
6526
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RS3-RSO
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DATA IN
DB7-DBO
6526 READ TIMING DIAGRAM
~2 INPUT
PORT IN
RS3-RSO
RIW
DATA OUT
DB7-DBO
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6526 INTERFACE SIGNALS
912 - Clock Input
The 02 clock is a TTL compatible input used for
internal device operation and as a timing reference for
communicating with the system data bus.
CS - Chip Select Input
The CS input controls the activity of the 6526. A low
level on CS while 02 is high causes the device to
respond to signals on the RNV and address (RS) lines.A
high on CS prevents these lines from controlling the
6526. The CS line is normally activated (low)at¢2 by the
appropriate address combination.
R/W - Read/Write Input
The RNV signal is normally supplied by the micro-
processor and controls the direction of data transfers of
the 6526. A high on RNV indicates a read (data transfer
out of the 6526), while a low indicates a write (data
transfer into the 6526).
RS3-RSO - Address Inputs
The address inputs select the internal registers as
described by the Register Map.
DB7-BDO - Data Bus Inputs/Outputs
The eight data bus pins transfer information between
the 6526 and the system data bus. These pins are high
impedance inputs unless CS is low and RNV and.02 are
high, to read the device. During this read, the data bus
output buffers are enabled, driving the data from the
selected register onto the system data bus.
IRQ - Interrupt Request Output
IRQ is an open drain output normally connected to
the processor interrupt input. An external~up resistor
holds the signal high, allowin.9...!:!1ultiple IRQ outputs to
be connected together. The IRQ output is normally off
(high impedance) and is activated low as indicated in
the functional description.
RES - Reset ~ut
A Iowan the RES pin resets all internal registers. The
port pins are set as inputs and port registers to zero
(although a read of the ports will return all highs
because of passive pullups). The timer control registers
are set to zero and the timer latches to all ones. All other
registers are reset to zero.
2-87

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6526 전자부품, 판매, 대치품
MPS
6526
from one stage to the next can occur at any time with
respect to a read operation, a latching function is
included to keep all Time Of Day information constant
during a read sequence. All four TOO registers latch
on a read of Hours and remain latched until after a
read of 1Oths of seconds. The TOO clock continues to
count when the output registers are latched. If only one
register is to be read, there is no carry problem and the
register can be read "on the fly," provided that any read
of Hours is followed by a read of 1Oths of seconds to
disable the latching.
READ
REG NAME
8 TOO 10THS
9 TOO SEC
A TOO MIN
B TOO HR
0
0
0
PM
000
SH4 SH2 SH1
MH4 MH2 MH1
0 0 HH
Ta
SLa
MLa
HLa
T4
SL4
ML4
HL4
T2
SL2
ML2
HL2
T1
SL1
ML1
HL1
WRITE
CRB7=O TOO
CRBr1 ALARM
(SAME FORMAT AS READ)
Serial Port (SDR)
The serial port is a buffered, 8-bit synchronous shift
register system. A control bit selects input or output
mode. In input mode, data on the SP pin is shifted into
the shift registeron the rising edge of the signal
applied to the CNT pin. After 8 CNT pulses, the data in
the shift register is dumped into the Serial Data
Register and an interrupt is generated. In the output
mode, TIMER A is used for the baud rate generator.
Data is sh ifted out on the SP pi nat V2 the underflow rate
of TIMER A. The maximum baud rate possible is ¢2
divided by 4, but the maximum useable baud rate will
be determined by line loading and the speed at which
the receiver responds to input data. Transmission will
start following a write to the Serial Data Register
(provided TIMER A is running and in continuous
mode). The clock Signal derived from TIMER A ap-
pears as an output on the CNT pin. The data in the
Serial Data Register will be loaded into the shift
register then shift out to the SP pin when a CNT pulse
occurs. Data shifted out becomes valid on the falling
edge of CNT and remains valid until the next falling
edge. After 8 CNT pulses, an interrupt is generated to
indicate more data can be sent. If the Serial Data
Register was loaded with new information prior to this
interrupt, the new data will automatically be loaded
into the shift register and transmission will continue. If
the microprocessor stays one byte ahead of the shift
register, transmission will be continuous. If no further
data is to be transmitted, after the 8th CNT pulse, CNT
will return high and SP will remain at the level of the last
data bit transmitted. SDR data is shifted but MSB first
and serial input data should also appear in this format.
The bidirectional capability of the Serial Port and
CNT clock allows many 6526 devices to be con-
nected to a common serial communication bus on
which one 6526 acts as a master, sourcing data and
shift clock, while all other 6526 chips act as slaves. Both
CNT and SP outputs are open drain to allow such a
common bus. Protocol for master/slave selection can
be transmitted over the serial bus, or via dedicated
handshaking lines.
Interrupt Control (ICR)
There are five sources of interrupts on the 6526:
underflow from TIMER A, underflow from TIMER B,
TODALARIv1,Serial Portfull/emptyand FLAG.Asingle
register provides masking and interrupt information.
The Interrupt Control Register consists of a write-only
MASK register and a read-only DATA register. Any
interrupt will set the corresponding bit in the DATA
register. Any interrupt which is enabled by the MASK
register will set the IR bit (MSB) of the DATA register
and bring the IRQ pin low. In a mu'iti-chip system, the
IR bit can be polled to detect which chip has gener-
ated an interrupt re~t. The interrupt DATA register
is cleared and the IRQ line returns high following a
read of the DATA register. Since each interrupt sets an
interrupt bit regardless of the MASK, and each inter-
rupt bit can be selectively masked to prevent the
generation of a processor interrupt, it is possible to
intermix polled interrupts with true interrupts. However,
polling the IR bit will cause the DATA register to clear,
therefore, it is up to the user to preserve the informa-
tion contained in the DATA register if any polled
interrupts were present.
The MASK register provides convenient control of
individual mask bits. When writing to the MASK regis-
ter, if bit 7 (SET/CLEAR) of the data written is a ZERO,
any mask bit written with a one will be cleared, while
those mask bits written with a zero will be unaffected. If
bit 7 of the data written is a ONE, any mask bit written
with a one will be set, while those mask bits written with
a zero will be unaffected. In order for an interrupt flag to
set IR and generate an Interrupt Request, the corre-
sponding MASK bit must be set.
READ (lNT DATA)
REG NAME
I I0 ICR IR
0
I0
I I IFLG sp ALRMI TB
TA
WRITE (lNT MASK)
IREG NAME
0 ICR SIC I X I x
FLGI SP IALRMI TB
ITA
2-90

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