PDF 6532 Data sheet ( Hoja de datos )

Número de pieza	6532
Descripción	MEMORY / TIMER ARRAY
Fabricantes	Commodore
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No Preview Available ! ,..,commodore ~ aernlconduct:or group [K!J~@~ MPS 6532 MEMORY, I/O, TIMER ARRAY 6532 (MEMORY, 110, TIMER ARRAY) THE 8532 CONCEPT- The 6532 Is designed to operate In conjunction with the MCS650X Microprocessor Family. It is comprised of a 128 x 8 static RAM, two software controlled 8 bit bl-dlrectional data ports allowing direct Interfacing between the microprocessor unit and peripheral devices, a software programmable Interval timer with Interrupt capable of timing In various Intervals from 1 to 262,144 clock periods, and a programmable edge detect circuit. FEATURES OF THE 8532 • 8 bit bl-dlrectlonal Data Bus for direct communication with the microprocessor • Programmable edge-sensitive Interrupt • 128 x 8 static RAM • Two 8 bit bl-dlrectlonal data ports for Interface to peripherals • Two programmable 110 Peripheral Data Direction Registers • Programmable Interval Timer • Programmable Interval Timer Interrupt • TTL & CMOS compatible. peripheral lines • Peripheral pins with Direct Transistor Drive Capability • High Impedance Three-State Data Pins • 1MHz, 2MHz and 3MHz operation ORDERING INFORMATION MXS6532_~ FREQUENCY RANGE NO SUFFIX = 1 MHz A = 2 MHz L...-_ _ _ _ _ _ PACKAGE DESIGNATOR C=CERAMIC P= PLASTIC 8532 PIN DESIGNATION vss .0.5 .0.4 "3 "2 AI AD PAD p.o., PA2 PA3 PA4 PA5 PA6 PA7 P87 P86 P85 PB4 VOO .0.6 02 CSI CS2 liS R/W REs OBO DB, DBz OB3 DB4 085 086 OB7 I"RQ PBO P81 PBZ PB3 2-107 1 page MPS 6532 WRITE TIMING CHARACTERISTICS CHARACTERISTIC Clock Period Rise & Fall Times Clock Pulse Width R/W valid before positive transition of clock Address valid before positive transition of clock Data Bus valid before negative transition of clock Data Bus Hold Time Peripheral data valid after negative transition of clock Peripheral data valid after negative transition of clock driving CMOS (Level=VCC-30%) SYMBOL TCYC TR, TF TC TWCW TACW TDCW THW TCPW TCMOS 1MHz MIN 1 - .470 MAX 20 25 10 -180 1130 - aoo - 10 - -1 -2 2MHz MIN MAX .5 10 - 25 .235 5 90 - 90 - 150 - 10 - - .500 -1 3MHz MIN MAX 0.33 10 - 25 0.160 5 60 - 60 - -100 10 - - .333 - .666 UNIT fJS nS fJS nS nS nS nS fS }JS I READ TIM ING CHARACTERISTICS 1MHz 2MHz 3MHz CHARACTERISTIC SYMBOL MIN MAX MIN MAX MIN MAX UNIT R/W valid before positive transition of clock TWGR 180 - 90 - 60 - nS Address valid before positive transition of clock TACR 180 - 90 - 60 - nS Peripheral data valid before positive transition of clock TPCR 300 - 150 - 100 - nS Data Bus valid after positive transition of clock Data Bus Hold Time TCDR THR - 400 - 200 - 135 nS 10 - 10 - 10 - nS IRQ valid before positive transition of clock TIC 200 - 100 - 75 - nS Loading = 30 pf + 1 TTL load 2-111 5 Page

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