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PDF 6545-1 Data sheet ( Hoja de datos )
| Número de pieza | 6545-1 | |
| Descripción | CRT Controller | |
| Fabricantes | Commodore | |
| Logotipo |  |
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,..,commodore
~ aernlcanductoor group
~UYAJ@@
MPS
6545-1
CRT
CONTROLLER
(CRTC)
6545-1 CRT Controller (CRTC)
CONCEPT
The 6545-1 is a CRT Controller intended to provide capability for interfacing the 6500/6800
microprocessor families to CRT or TV-type raster scan displays. A unique feature is the inclusion of
several modes of operation, so that the system designer can configure the system with a wide
assortment of techniques.
FEATURES:
• Single +5 volt (±5%) power supply.
• Alphanumeric and limited graphics
capabi Iities.
• Fully programmable display (rows, columns,
blanking, etc.).
• Non-interlaced scan.
.50/60 Hz operation.
• Fully programmable cursor.
• External light pen capability.
• Capable of addressing up to 16K character
video display RAM.
• No DMA required.
• Pin-compatible with MC6845.
• Row/Column or straight-binary addressing
for video display RAM.
• Internal 8-bit status register.
I
ORDERING INFORMATION
MXS 6545-1 1 MHz
MXS 6545A-1 2 MHz
- - - - PACKAGE DESIGNATOR
C = CERAMIC
P = PLASTIC
6545-1 PIN DESIGNATION
GNO
RES
LPEN
CCO/MAO
CC1/MAl
CC2/MA2
CC3/MA3
CC4/MA4
CC5/MA5
CC6/MA6
CC7/MA7
CRO/MA8
CR1/MA9
CR2/MA10
CR3/MA11
CR4/MA12
CR5/MA13
DISPLAY ENA8LE
CURSOR
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VSYNC
39 HSYNC
38 RAO
37 RAl
36 RA2
35 RA3
34 RA4
33 080
32 081
31 082
30 083
29 084
28 085
27 086
26 087
25 CS
24 RS
23 !1\2
22 R/w
21 CCLK
2-117
1 page  
MPS
6545-1
MEMORY AND VIDEO INTERFACE CHARACTERISTICS
(Vee - 5.av ± 5%, TA = a to 7aoe, unless otherwise noted)
Output
Parameter
SYSTEM TIMING
MAO-MA13
RAO-RA4
DISPLAY-ENABLE
HSYNC
VSYNC
CURSOR
tMAD
tRAD
tOTO
tHSD
tvSD
tCDD
SYSTEM TIMING PARAMETERS (Vee = 5.aV + 5%, TA = a to 7aoe, unless otherwise noted)
6545-1
6545A-1
Symbol Characteristics
Min.
Max.
Min.
Max.
Unit
tCCY
tCCH
tMAD
Character Clock Cycle Time
Character Clock Pulse Width
MAO-MA 13 Propagation Delay
0040 40 OAO 40
200 -
200 -
- 300 - 300
/-ls
ns
ns
tRAD
RAO-RA4 Propagation Delay
- 300 - 300 ns
tOTO
DISPLAY ENABLE Propagation Delay
- 375 -
375 ns
tHSD
tvSD
tCDD
tLPH
HSYNC Propagation Delay
VSYNC Propagation Delay
CURSOR Propagation Delay
LPEN Hold Time
- 375 -
- 375 -
375 ns
375 ns
- 375 - 375 ns
100 -
100 -;-
ns
tLP1
tLP2
LPEN Set-up Time
CCLK to LPEN Delay
20 -
0-
20 -
0-
ns
ns
tr, tf == 20 ns (max)
LIGHT PEN STROBE TIMING DEFINITIONS
CCLK
I
LPEN
______________ _______MAO-MA13
~X~
n_+_l_ _ _ _~)(~_ _ _ _ _ _ _n_+_2_ _ _ _~)(~_ _ _ _ _ __ _
NOTE: "Safe" time position for LPEN positive edge to cause
address n+2 to load into Light Pen Register.
tLP2 and tLPl are time positions causing uncertain results.
2-121
5 Page 
MPS
6545-1
DETAILED DESCRIPTION OF OPERATION
Register Formats
Register pairs R12/R13, R14/R15, and R16/R17 are for-
matted in one of two ways:
1. Straight binary if register R8, bit 2 is a "0".
2. Row/Column if register R8,bit2 isa "1 ".Inthiscasethe
low byte is the Character Column and the high byte is
tt,e Character Row.
Figure 4 illustrates the address sequence for the video
display control for each mode.
Note from Figure 4 that the straight-binary mode has the
advantage that all display memory addresses are stored in a
continuous memory block, starting with address 0 and
ending at 1919. The disadvantage with this method is that, if
it is desired to change a displayed character location, the
row and column identity of the location must be converted to
its binary address before the memory may be written. The
row/column mode, on the other hand, does not need to
undergo this conversion. However, memory is not used as
efficiently, since the memory addresses are not continuous,
but gaps exist. This requires that the system be equipped
with more memory than is actually used and this extra
memory is wasted. Alternatively, address compression logic
may be employed to translate the row/column format into a
continuous address block.
---lI TOTAL - 90 -----
iDISPLAY-80---1
I
iT : :;, :, :: : :.:,:: :, ::
;'; :::i
I~
« L-' is
1760 1761 1762
f-
--1---- '-
••• 1837 fl838 1839 18401841
1849
~ 18401141 1842.
• •• 1917 1918 1919 1920 1921
1929
'0'000 ,'0092,' "'002 22 .•• ... 1997 1999 1999 ~ ~~~ ." 2_~
2077 2018 2079 2080 208' ... 2089
"~4--+-f-+--+~~+--+~-~- I--.~
L 2~9L26-4-0'-2-6-41-'-26_4L2 -..L-,-.-, -'-27_17L2.7.1.8-'-27_19-'-2_72_0'-2-72_1 ___ _
In this way, the user may select whichever mode is best for
the given application. The trade-ofts between the modes are
software versus hardware. Straight-binary mode minimizes
hardware requirements and row/column requires minimum
software.
Memory Contention Schemes
for Memory Addressing
From the diagram of Figure 4, it is clear that both the 6545-1
and the system MPU must be capable of addressing the
video display memory. The 6545-1 repetitively fetches
character information to generate the video signals in order
to keep the screen display active. The M PU occasionally
accesses the memory to change the displayed information
or to read out current data characters. Three ways of
resolving this dual-contention requirements are apparent:
• MPU Priority
In this technique, the address lines to the video display
memory are normally driven by the 6545-1 unless the
MPU needs access, in which case the MPU addresses
immediately override those from the 6545-1 and the
M PU has immediate access.
• 01/02 Memory Interleaving
This method permits both the 6545-1 and the M PU
access to the video display memory by time-sharing via
the system 01 and 02 clocks. During the 01 portion of
each cycle (the time when (1.\2 is low), the 6545-1 address
--l~ -TOTAL-90--- -
~ COLUMN ADDRESS (MAO-MA7) --~
- - - I- - - DISPLAY - 80
I
Io , 2
-1
I G4,F)
1
0I~0 '' 2"8
4: ~ 2 ~ 513 !l14 -.~-~--
i~ I .:
I77 78 79 eo
89
,77~
18
>34
f~' .t-;;8 0~
.'--'---l~.
-;-31 -
+-".589 590 59~ 592 593
:601
: --+--t---r,
~ ~ ~ : 1-;--1-- f-I- I----+---'--J--
'I ~ ~ . .
g...J cr: 0 22 ~~~!~
0 ~ ~888 ~889 5890 •..
I- ~
614~24 6144
6146
L~ 2:!J 64:00 MOl 6402
~8448844984'0'"
f-~= --~. -~=--'-t- ..
.. 5109 5710 5711 5712 5713
_
~".7_-=-~
..• 5965 ~966 ~96 !l968 ~969 ... ••
622~~ ~~••• 6221 6222 6223 6224
..
...~~~~~~~~~ 6481 •.. ;~
"._. 8"'B.2~~..".""~
STRAIGHT BINARV ADDRESSING SEQUENCE
ROW/COLUMN ADDRESSING SEQUENCE
Figure 4. Display Address Sequences (with Start Address = 0) for 80 x 24 Example
I
I MPU
SYSTEM
BUS
F
.1 6545-1
HVSYNNCC
~
A
MPU
CRT CONTROLLER
'I MAO-MA13
o DISPLAY ADDRESS
RAO-RA4
I IADDRESS
CONTENTION
I CONTROL
SCAN LINE
COUNT
~PLAY ENABLE
I SHIFT
REGISTER
I
r
ADDRESS
BUS
" .1
MPU '1
DATE
BUS
tl
VIDEO
DISPLAY
1
"
RAM
I CHARACTER
DATA
'"_m' ~,.1
I GENERATOR
ROM
SCAN LINE
DOT PATTERN
}
Figure 5. Typical System Configuration
2-127
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet 6545-1.PDF ] | |
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