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PDF AT84CS001 Data sheet ( Hoja de datos )
| Número de pieza | AT84CS001 | |
| Descripción | 10-bit 2.2 Gsps 1:4 DMUX | |
| Fabricantes | e2v | |
| Logotipo |  |
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AT84CS001
10-bit 2.2 Gsps 1:4 DMUX
Datasheet
Features
• High-speed ADC Family Companion Chip
• Selectable 1:2 or 1:4 DMUX Ratio
• Power Consumption: 2.7W
• LVDS Compatible Differential Data and Clock Inputs (100Ω Terminated)
• LVDS Compatible Differential Data and Data Ready Outputs
• Staggered or Simultaneous Data Outputs
– 11th Bit = Ports A, B, C and D Clock in Staggered Mode
• Selectable Active Edge for Input and Output Clocks:
– Only Rising: CLK and DR Mode
– Rising and Falling: CLK/2 and DR/2 Mode
• Fine Tuning of Input Clock Path Delay
– Compensation of External Data and Clock Path Misalignment and Skews
– Once Tuned, Setting is Valid over Full Operating Frequency and Over Full Specified Temperature Range
• Additional 11th Bit (Example: for Out-of-range Bit)
• Built-in Self Test (BIST)
• Stand-alone Tunable Delay Cell
• Power Supplies: VCCD = 3.3V (Digital), VPLUSD = 2.5V (Outputs)
• Power Consumption Reduction Mode: 1.15W
• EBGA240 Package
Screening
• Temperature Range:
– - 40°C < TC; TJ < 110°C (Industrial Grade)
Applications
This DMUX enables users to process high-speed output data streams from fast analog-to-digital converters down to stan-
dard FPGA processor speed.
Description
The AT84CS001 is a monolithic high-speed demultiplexer, used to lower a 10-bit data stream of up to 2.2 Gsps guaranteed
rate by a selectable 4 or 2 ratio (a 1:8 ratio might be achieved by interleaving two DMUXes).
The DMUX is a companion chip designed to fit perfectly with all of e2v’s high-speed ADCs and is capable of tracking the
ADC’s output sampling rate over all operating frequency and temperature ranges.
Thanks to its LVDS buffers, this DMUX can easily be interfaced with standard high-speed FPGAs (100Ω differentially
terminated).
The AT84CS001 has the same footprint as e2v’s TS81102G0 DMUX, with a very similar pinout. Minimum re-design efforts
are required to use this low-power DMUX. An application note Migration from AT84AS008 to EV10AS008B reference 0810,
is available to assist in migrating from the TS81102G0 to the AT84CS001.
e2v semiconductors SAS 2009
Visit our website: www.e2v.com
for the latest version of the datasheet
0809E–BDC–05/09
1 page  
AT84CS001
Figure 3-1. Device Pinout
[I0…I9]
[I0N…I9N]
CLK, CLKN
20
2
ASYNCRST
DACTRL
CLKDACTRL
DAI, DAIN
2
SLEEP
STAGG
CLKTYPE
RS
DAEN
BIST
DRTYPE
VCCD
VPLUSD
AT84CS001
20 [A0…A9]
[A0N…A9N]
2 AOR/DRAN
AORN/DRA
20 [B0…B9]
[B0N…B9N]
2 BOR/DRBN
BORN/DRB
20 [C0…C9]
[C0N…C9N]
2 COR/DRCN
CORN/DRC
20 [D0…D9]
[D0N…D9N]
2 DOR/DRDN
2 DORN/DRD
DAO, DAON
2
DR, DRN
GND
3.1 Control Signal Settings
The ASYNCRST, SLEEP, DAEN, STAGG, BIST, RS, CLKTYPE and DRTYPE control signals use the
same static input buffer.
ASYNCRST is activated on logic HIGH (tied/switched to VCCD = 3.3V, or 10 kΩ to ground, or left float-
ing), and deactivated on logic LOW (grounded).
SLEEP, DAEN, STAGG, BIST are activated on logic LOW (10Ω grounded), and deactivated on logic
HIGH (10 kΩ to ground, or tied to VCCD = 3.3V, or left floating).
Figure 3-2. Control Signal Settings
Control
10Ω Signal Pin
10 KΩ
Control
Signal Pin
Not
Connected
Control
Signal Pin
GND
Active Low Level ('0')
GND
Inactive High Level ('1')
e2v semiconductors SAS 2009
0809E–BDC–05/09
5
5 Page 
AT84CS001
3.7 Power Reduction Mode (SLEEP)
The power reduction mode saves up to 60% of power consumption. In this mode, the DMUX delivers an
arbitrary digital output pattern with LVDS logic states (no toggling).
The power reduction mode is enabled by the SLEEP input. SLEEP is activated on logic LOW
(grounded), and deactivated on logic HIGH (10 KΩ to Ground, or tied to VCCD = 3.3V, or left floating).
3.8 Standalone Delay Cell (DAI, DAIN) (DAO, DAON)
A standalone tunable delay cell is provided. The delay line is controlled via the DACTRL analog control
input. The tuning range is about 550 ps for DACTRL varying from VCCD / 3 to (2 × VCCD)/ 3.
The (DAI, DAIN) and (DAO, DAON) are LVDS compatible input and output respectively. The Standalone
Delay Cell is enabled by the DAEN input.
DAEN is activated on Logic Low (Grounded), and deactivated on Logic High (10 KΩ to ground, or tied to
VCCD = 3.3V, or left floating).
Figure 3-10. Block Diagram of the Standalone Delay Cell
(DAI, DAIN)
2
Delay
2
(550 ps tuning range)
(DAO, DAON)
DACTRL
DAEN (active LOW)
e2v semiconductors SAS 2009
0809E–BDC–05/09
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT84CS001.PDF ] | |
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