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AT84AD004B 데이터시트 PDF




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부품번호 AT84AD004B 기능
기능 Dual 8-bit 500 Msps ADC
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AT84AD004B 데이터시트, 핀배열, 회로
Datasheet
AT84AD004B
Dual 8-bit 500 Msps ADC
1. Features
Dual ADC with 8-bit Resolution
500 Msps Sampling Rate per Channel, 1 Gsps in interleaved Mode
Single or 1:2 Demultiplexed Output
LVDS Output Format (100Ω)
500 mVpp Analog Input (Differential Only)
Differential or Single-ended 50Ω PECL/LVDS Compatible Clock Inputs
Power Supply: 3.3V (Analog), 3.3V (Digital), 2.25V (Output)
LQFP144 or LQFP-ep 144L Green packages
Temperature Range:
– 0°C < Tamb < 70° C (Commercial Grade)
– –40°C < Tamb < 85° C (Industrial Grade)
3-wire Serial Interface
– 16-bit Data, 3-bit Address
– 1:2 or 1:1 Output Demultiplexer Ratio Selection
– Full or Partial Standby Mode
– Analog Gain (±1.5 dB) Digital Control
– Input Clock Selection
– Analog Input Switch Selection
– Binary or Gray Logical Outputs
– Synchronous Data Ready Reset
– Data Ready Delay Adjustable on Both Channels
– interleaving Functions:
• Offset and Gain (Channel to Channel) Calibration
• Digital Fine SDA (Fine Sampling Delay Adjust) on One Channel
– Internal Static or Dynamic Built-In Test (BIT)
2. Performance
Low Power Consumption: 0.7W per Channel
Power Consumption in Standby Mode: 120 mW
1 GHz Full Power Input Bandwidth (–3 dB)
SNR = 45 dB Typ (7.2 ENOB), THD = –53 dBc, SFDR = –56 dBc at Fs = 500 Msps
Fin = 250 MHz
2-tone IMD3: –54 dBc (249 MHz, 251 MHz) at 500 Msps
DNL = 0.25 LSB, INL = 0.5 LSB
Low Bit Error Rate (10–18) at 500 Msps
e2v semiconductors SAS 2009
Visit our website: www.e2v.com
for the latest version of the datasheet
0818F–BDC–09/09




AT84AD004B pdf, 반도체, 판매, 대치품
AT84AD004B
6. Typical Applications
Figure 6-1. Satellite Receiver Application
Satellite
Dish
Low Noise Converter
(Connected to the Dish)
Bandpass
Amplifier
Bandpass
Amplifier
11..12 GHz
1..2 GHz
Local Oscillator
Low Pass
Filter
Satellite Tuner
Tunable
Band Filter
IF
Band Filter
Synthesizer
1.5 … 2.5 GHz
AGC
I
II
Control Functions:
Clock and Carrier
AT84AD004
Local Oscillator
0
90
Recovery...
Q
Q Q Clock
Q
Quadrature
Demodulation
4
0818F–BDC–09/09
e2v semiconductors SAS 2009

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AT84AD004B 전자부품, 판매, 대치품
AT84AD004B
Table 7-1. Electrical Operating Characteristics in Nominal Conditions (Continued)
Parameter
Symbol Min Typ
Supply current
(1 channel only, 1:1 DMUX mode)
- Analog
- Digital
- Output
Supply current
(1 channel only, 1:2 DMUX mode)
- Analog
- Digital
- Output
ICCA
ICCD
ICCO
ICCA
ICCD
ICCO
Supply current (full standby mode)
- Analog
- Digital
- Output
Nominal dissipation
(1 clock, 1:1 DMUX mode, 2 channels)
ICCA
ICCD
ICCO
PD
Nominal dissipation (full standby mode)
stbpd
Analog Inputs
Full-scale differential analog input voltage to
obtain full-scale with no gain adjust (mode 0)
Analog input common mode
VINi – VIniB
or
VINQ – VINQB
Analog input capacitance I and Q
Full power input bandwidth (–3 dB)
CIN
FPBW
Gain flatness (–0.5 dB)
Clock Input
Logic compatibility for clock inputs and DDRB
Reset (pins 124,125,126,127,128,129)
PECL/LVDS clock inputs and DDRB input
voltages (VCLKI/IN or VCLKQ/QN)
Differential logical level
VIL – VIH
Clock input and DDRB input power level
Clock input capacitance
Digital Outputs (including DOIRI, DOIRIN, DOIRQ and DOIRQN signals)
Logic compatibility for digital outputs
(depending on the value of VCCO)
Differential output voltage swings
(assuming VCCO = 2.25V)
Output levels (assuming VCCO = 2.25V)
100Ω differentially terminated
Logic 0 voltage
Logic 1 voltage
VOD
VOL
VOH
80
160
55
80
170
90
12
24
3
1.4
120
450 500
0
1.0
400
PECL/ECL/LVDS
600
–9 0
2
LVDS
220 270
1.0 1.1
1.25 1.35
Max
95
190
65
95
205
110
20
39
7
1.7
550
2
6
350
1.2
1.48
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
W
mW
mV
mV
V
pF
GHz
MHz
mV
dBm
pF
mV
V
V
e2v semiconductors SAS 2009
0818F–BDC–09/09
7

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