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PDF P89LPC9321 Data sheet ( Hoja de datos )
| Número de pieza | P89LPC9321 | |
| Descripción | 8-bit microcontroller | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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P89LPC9321
8-bit microcontroller with accelerated two-clock 80C51 core
8 kB 3 V byte-erasable flash with 512-byte data EEPROM
Rev. 2 — 16 November 2010
Product data sheet
1. General description
The P89LPC9321 is a single-chip microcontroller, available in low cost packages, based
on a high performance processor architecture that executes instructions in two to four
clocks, six times the rate of standard 80C51 devices. Many system-level functions have
been incorporated into the P89LPC9321 in order to reduce component count, board
space, and system cost.
2. Features and benefits
2.1 Principal features
8 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte pages.
Single-byte erasing allows any byte(s) to be used as non-volatile data storage.
256-byte RAM data memory and a 512-byte auxiliary on-chip RAM.
512-byte customer data EEPROM on-chip allows serialization of devices, storage of
setup parameters, etc.
Two analog comparators with selectable inputs and reference source.
Single Programmable Gain Amplifier (PGA) with selectable gains of 2x, 4x, 8x, or 16x
can be applied to analog comparator inputs.
Two 16-bit counter/timers (each may be configured to toggle a port output upon timer
overflow or to become a PWM output).
A 23-bit system timer that can also be used as real-time clock consisting of a 7-bit
prescaler and a programmable and readable 16-bit timer.
Enhanced UART with a fractional baud rate generator, break detect, framing error
detection, and automatic address detection; 400 kHz byte-wide I2C-bus
communication port and SPI communication port.
Capture/Compare Unit (CCU) provides PWM, input capture, and output compare
functions.
2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
4-level low voltage (brownout) detect allows a graceful system shutdown when power
fails. May optionally be configured as an interrupt.
28-pin TSSOP, PLCC and DIP packages with 23 I/O pins minimum and up to 26 I/O
pins while using on-chip oscillator and reset options.
1 page  
NXP Semiconductors
5. Functional diagram
P89LPC9321
8-bit microcontroller with accelerated two-clock 80C51 core
KBI0
KBI1
KBI2
KBI3
KBI4
KBI5
KBI6
KBI7
CLKOUT
CMP2
CIN2B
CIN2A
CIN1B
CIN1A
CMPREF
CMP1
T1
XTAL2
XTAL1
PORT 0
PORT 3
Fig 2. Functional diagram
VDD VSS
P89LPC9321
002aae103
PORT 1
PORT 2
TXD
RXD
T0
INT0
INT1
RST
OCB
OCC
SCL
SDA
ICB
OCD
MOSI
MISO
SS
SPICLK
OCA
ICA
P89LPC9321
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 November 2010
© NXP B.V. 2010. All rights reserved.
5 of 71
5 Page 
NXP Semiconductors
P89LPC9321
8-bit microcontroller with accelerated two-clock 80C51 core
7. Functional description
Remark: Please refer to the P89LPC9321 User manual for a more detailed functional
description.
7.1 Special function registers
Remark: SFR accesses are restricted in the following ways:
• User must not attempt to access any SFR locations not defined.
• Accesses to any defined SFR locations must be strictly for the functions for the SFRs.
• SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:
– ‘-’ Unless otherwise specified, must be written with ‘0’, but can return any value
when read (even if it was written with ‘0’). It is a reserved bit and may be used in
future derivatives.
– ‘0’ must be written with ‘0’, and will return a ‘0’ when read.
– ‘1’ must be written with ‘1’, and will return a ‘1’ when read.
P89LPC9321
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 16 November 2010
© NXP B.V. 2010. All rights reserved.
11 of 71
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