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부품번호 MC33932 기능
기능 5.0A Throttle Control H-Bridge
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MC33932 데이터시트, 핀배열, 회로
Freescale Semiconductor
Technical Data
Document Number: MC33932
Rev. 5.0, 10/2012
5.0 A Throttle Control H-Bridge
The 33932 is a monolithic H-Bridge Power IC in a robust thermally
enhanced package. The 33932 has two independent monolithic
H-Bridge Power ICs in the same package. They are designed primarily
for automotive electronic throttle control, but are applicable to any low
voltage DC servo motor control application within the current and
voltage limits stated in this specification.
Each H-Bridge in the 33932 is able to control inductive loads with
currents up to 5.0 A peak. RMS current capability is subject to the
degree of heatsinking provided to the device package. Internal peak-
current limiting (regulation) is activated at load currents above 6.5 A
±1.5 A. Output loads can be pulse-width modulated (PWM-ed) at
frequencies up to 11 kHz. A load current feedback feature provides a
proportional (0.24% of the load current) current output suitable for
monitoring by a microcontroller’s A/D input. A Status Flag output
reports under-voltage, over-current, and over-temperature fault
conditions.
Two independent inputs provide polarity control of two half-bridge
totem pole outputs. Two independent disable inputs are provided to
force the H-Bridge outputs to tri-state (high-impedance off state).
Features
• 8.0 to 28 V continuous operation (transient operation from 5.0 to
40 V)
• 235 mmaximum RDS(ON) at 150 °C (each H-Bridge MOSFET)
• 3.0 and 5.0 V TTL / CMOS logic compatible inputs
• Output short-circuit protection (short to VPWR or GND)
• Over-current limiting (regulation) via internal constant-off-time
PWM
• Temperature dependant current limit threshold reduction
• All inputs have an internal source/sink to define the default
(floating input) states
• Sleep mode with current draw < 50 µA (each half with inputs
floating or set to match default logic states)
VDD
33932
THROTTLE CONTROL H-BRIDGE
VW SUFFIX (PB-FREE)
98ARH98330A
44-PIN HSOP
WITH PROTRUDING
HEAT SINK
EK SUFFIX (PB-FREE)
98ASA99334D
54-PIN SOICW-EP
ORDERING INFORMATION
Device
(Add R2 Suffix for
Tape and Reel)
Temperature
Range (TA)
Package
MC33932VW
MC33932EK
-40 to 125 °C
44 HSOP
54 SOICW-EP
VPWR
MCU
VDD
33932
SFA
FBA
VPWRA
CCPA
OUT1
IN1
IN2
D1
EN/D2
IN3
IN4
D3
EN/D4
FBB
OUT2
PGNDA
AGNDA
VPWRB
CCPB
OUT3
SFB
PGNDB
AGNDB
OUT4
MOTOR
VPWR
MOTOR
Figure 1. MC33932 Simplified Application Diagram
© Freescale Semiconductor, Inc., 2009-2012. All rights reserved.




MC33932 pdf, 반도체, 판매, 대치품
PIN CONNECTIONS
Table 1. 33932 Pin Definitions (continued)
Pin
HSOP
(VW)
Pin
SOICW-EP Pin Name
(EK)
10, 11, 34, 12, 13, 42, PGNDA
35 43
Pin
Function
Power
Ground
Formal Name
Power Ground
Definition
High-current power ground pins must be connected together
physically as close as possible and directly soldered down to a
wide, thick, low resistance ground plane on the PCB. PGNDA
should be connected to PGNDB with a low-impedance path.
12, 13, 32, 15, 16, 39, PGNDB
33 40
Power
Ground
Power Ground
High-current power ground pins must be connected together
physically as close as possible and directly soldered down to a
wide, thick, low resistance ground plane on the PCB. PGNDB
should be connected to PGNDA with a low-impedance path.
14-16
17, 18,
26-28
17, 18
19, 26, 28,
36
OUT4
VPWRB
Power
Output
H-Bridge Output 4
Power Input Positive Power
Supply
H-Bridge B Source of HS2 and drain of LS2.
These pins must be connected together physically as close as
possible and directly soldered down to a wide, thick, low
resistance supply plane on the PCB.
19
20
CCPB
Analog
Charge Pump External reservoir capacitor connection for H-Bridge B internal
Output
Capacitor
charge pump; connected to VPWRB. Allowable values are 30 to
100 nF. Note: This capacitor is required for the proper
performance of the device.
20
23
IN4 Logic Input
Input 4
Logic input control of OUT4.
21
24
IN3 Logic Input
Input 3
Logic input control of OUT3.
22
25
SFB
Logic
Status Flag B
H-Bridge B open drain active LOW Status Flag output (requires
Output -
Open Drain
(Active Low)
an external pull-up resistor to VDD. Maximum permissible load
current < 0.5 mA. Maximum VSFLOW < 0.4 V at 0.3 mA. Maximum
permissible pull-up voltage < 7.0 V.)
23 30 D3 Logic Input Disable Input 3 When D3 is logic HIGH, both OUT3 and OUT4 are tri-stated.
(Active High)
Schmitt trigger input with ~80 A source so default condition =
disabled.
24
31
FBB
Analog
Feedback B
H-Bridge B load current feedback output provides ground
Output
referenced 0.24% of the high side output current. (Tie to GND
through a resistor if not used.)
25
29-31
36-38
41
32
37, 38
44, 45
47
EN/D4
OUT3
OUT2
CCPA
Logic Input
Power
Output
Power
Output
Analog
Output
Enable Input
H-Bridge Output 3
H-Bridge Output 2
Charge Pump
Capacitor
When EN/D4 is logic HIGH, H-Bridge B is operational. When EN/
D4 is logic LOW, the H-Bridge B outputs are tri-stated and H-
Bridge B is placed in Sleep Mode. (logic input with ~80A sink so
default condition = Sleep Mode.)
H-Bridge B Source of HS1 and drain of LS1.
H-Bridge A source of HS2 and drain of LS2.
External reservoir capacitor connection for H-Bridge A internal
charge pump; connected to VPWRA. Allowable values are 30 to
100 nF. Note: This capacitor is required for the proper
performance of the device.
42
50
IN2 Logic Input
Input 2
Logic input control of OUT2.
43
51
IN1 Logic Input
Input 1
Logic input control of OUT1; e.g., when IN1 is logic HIGH, OUT1
is set to VPWRA, and when IN1 is logic LOW, OUT1 is set to
PGNDA. (Schmitt trigger Input with ~80 A source so default
condition = OUT1 HIGH.)
33932
4
Analog Integrated Circuit Device Data
Freescale Semiconductor

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MC33932 전자부품, 판매, 대치품
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 5.0 V VPWR 28 V, -40 C TA 125C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Specifications given for H-Bridge A apply symmetrically to H-Bridge B.
Characteristic
Symbol
Min Typ Max Unit
POWER INPUTS (VPWR)
Operating Voltage Range(10)
Steady-state
Transient (t < 500 ms)(11)
Sleep State Supply Current(12)
EN/D2 = Logic [0], IN1, IN2, D1 = Logic [1], and IOUT = 0 A
Standby Supply Current (Part Enabled)
IOUT = 0 A, VEN = 5.0 V
Under-voltage Lockout Thresholds
VPWR(FALLING)
VPWR(RISING)
Hysteresis
CHARGE PUMP
V
VPWR(SS)
5.0
28
VPWR(t)
– 40
IPWR(SLEEP)
A
– 50
IPWR(STANDBY)
mA
– 20
VUVLO(ACTIVE)
4.15
–V
VUVLO(INACTIVE)
– 5.0 V
VUVLO(HYS)
150
200
350
mV
Charge Pump Voltage (CP Capacitor = 33 nF), No PWM
VPWR = 5.0 V
VPWR = 28 V
Charge Pump Voltage (CP Capacitor = 33 nF), PWM = 11 kHz
VPWR = 5.0 V
VPWR = 28 V
VCP - VPWR
3.5
V
– – 12
VCP - VPWR
3.5
V
– – 12
CONTROL INPUTS
Operating Input Voltage (IN1, IN2, D1, EN/D2, IN3, IN4, D3, EN/D4)
Input Voltage (IN1, IN2, D1, EN/D2, IN3, IN4, D3, EN/D4)
Logic Threshold HIGH
Logic Threshold LOW
Hysteresis
Logic Input Currents, VPWR = 8.0 V
Input EN/D2, EN/D4 (internal pull-downs), VIH = 5.0 V
Inputs IN1, IN2, D1, IN3, IN4, D3 (internal pull-ups), VIL = 0 V
VI
VIH
VIL
VHYS
IIN
– – 5.5 V
2.0 –
–V
– – 1.0 V
250 400 – mV
A
20 80 200
-200
-80
-20
Notes
10. Device specifications are characterized over the range of 8.0 V VPWR 28 V. Continuous operation above 28 V may degrade device
reliability. Device is operational down to 5.0V, but below 8.0 V the output resistance may increase by 50 percent.
11. Device will survive the transient over-voltage indicated for a maximum duration of 500 ms. Transient not to be repeated more than once
every 10 seconds.
12. IPWR(SLEEP) is with Sleep Mode activated and EN/ D2, = logic [0], and IN1, IN2, D1 = logic [1] or with these inputs left floating.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33932
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