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PDF MPC972 Data sheet ( Hoja de datos )
| Número de pieza | MPC972 | |
| Descripción | LOW VOLTAGE PLL CLOCK DRIVER | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC972/D
Rev 6, 09/2001
Low Voltage PLL Clock Driver
The MPC972 is a 3.3 V compatible, PLL based clock driver device
targeted for high performance CISC or RISC processor based systems.
With output frequencies of up to 125 MHz and skews of 550 ps the MPC972
is ideally suited for most synchronous systems. The device offers twelve low
skew outputs plus a feedback and sync output for added flexibility and ease
of system implementation.
MPC972
• Fully Integrated PLL
• Output Frequency up to 125 MHz
• Compatible with PowerPC and Pentium Microprocessors
• LQFP Packaging
• 3.3 V VCC
LOW VOLTAGE
PLL CLOCK DRIVER
• ± 100 ps Typical Cycle–to–Cycle Jitter
The MPC972 features an extensive level of frequency programmability
between the 12 outputs as well as the input vs output relationships. Using
the select lines output frequency ratios of 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2,
5:3, 6:1 and 6:5 between outputs can be realized by pulsing low one clock
edge prior to the coincident edges of the Qa and Qc outputs. The Sync
output will indicate when the coincident rising edges of the above
relationships will occur. The selectability of the feedback frequency is
independent of the output frequencies, this allows for very flexible
programming of the input reference vs output frequency relationship. The
output frequencies can be either odd or even multiples of the input
reference. In addition the output frequency can be less than the input
SCALE 2:1
frequency for applications where a frequency needs to be reduced by a
non–binary factor. The Power–On Reset ensures proper programming if the
FA SUFFIX
frequency select pins are set at power up. If the fselFB2 pin is held high, it
may be necessary to apply a reset after power–up to ensure
52–LEAD LQFP PACKAGE
CASE 848D-03
synchronization between the QFB output and the other outputs. The internal
power–on reset is designed to provide this function, but with power–up
conditions being dependent, it is difficult to guarantee. All other conditions of
the fsel pins will automatically synchronize during PLL lock acquisition.
The MPC972 offers a very flexible output enable/disable scheme. This enable/disable scheme helps facilitate system debug as
well as provide unique opportunities for system power down schemes to meet the requirements of “green” class machines. The
MPC972 allows for the enabling of each output independently via a serial input port. When disabled or “frozen” the outputs will be
locked in the “LOW” state, however the internal state machines will continue to run. Therefore when “unfrozen” the outputs will
activate synchronous and in phase with those outputs which were not frozen. The freezing and unfreezing of outputs occurs only
when they are already in the “LOW” state, thus the possibility of runt pulse generation is eliminated. A power-on reset will ensure
that upon power up all of the outputs will be active. Note that all of the control inputs on the MPC972 have internal pull–up resistors.
The MPC972 is fully 3.3 V compatible and requires no external loop filter components. All inputs accept LVCMOS/LVTTL
compatible levels while the outputs provide LVCMOS levels with the capability to drive 50 Ω transmission lines. For series
terminated lines each MPC972 output can drive two 50 Ω lines in parallel thus effectively doubling the fanout of the device.
The MPC972 can consume significant power in some configurations. Users are encouraged to review Application Note
AN1545/D in the Advanced Clock Drivers Device Data book (DL207/D) for a discussion on the thermal issues with the MPC family
of clock drivers.
PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.
Motorola, Inc. 2001
t
1 page  
MPC972
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Min Max Unit
VCC Supply Voltage
–0.3 4.6 V
VI Input Voltage
–0.3
VCC + 0.3
V
IIN Input Current
±20 mA
TStor
Storage Temperature Range
–40 125 °C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied.
THERMAL CHARACTERISTICS
Proper thermal management is critical for reliable system operation. This is especially true for high fanout and high drive
capability products. Generic thermal information is available for the Motorola Clock Driver products. The means of calculating die
power, the corresponding die temperature and the relationship to long–term reliability is addressed in the Motorola application note
AN1545.
DC CHARACTERISTICS (Note 3.; TA = 0° to 70°C; VCC = 3.3 V ±5%)
Symbol
Characteristic
Min Typ Max Unit
Condition
VCCA
VIH
VIL
VOH
Analog VCC Voltage
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
2.935
2.0
2.4
VCC
3.6
V
V
0.8 V
V IOH = –20 mA (Note 1.)
VOL
IIN
ICC
ICCA
CIN
Output LOW Voltage
Input Current
Maximum Quiescent Supply Current
Analog VCC Current
Input Capacitance
0.5
±120
V IOL = 20 mA (Note 1.)
µA Note 2.
190 215 mA All VCC PIns
15 20 mA
4 pF
Cpd Power Dissipation Capacitance
25 pF Per Output
1. The MPC972 outputs can drive series or parallel terminated 50 Ω (or 50 Ω to VCC/2) transmission lines on the incident edge (see Applications
Info section).
2. Inputs have pull–up/pull–down resistors which affect input current.
3. Special thermal handling may be required in some configurations.
PLL INPUT REFERENCE CHARACTERISTICS (TA = 0° to 70°C)
Symbol
Characteristic
Min
Max Unit
Condition
tr, tf TCLK Input Rise/Falls
fref Reference Input Frequency
Note 4.
3.0
100
Note 4.
ns
MHz
frefDC
Reference Input Duty Cycle
25 75 %
txtal Crystal Oscillator Frequency
10 25 MHz Note 5.
4. Maximum input reference frequency is limited by the VCO lock range and the feedback divider or 100MHz, minimum input reference frequency
is limited by the VCO lock range and the feedback divider.
5. See Applications Info section for more crystal information.
MOTOROLA
5
5 Page 
3.0
OutA
2.5 tD = 3.8956
2.0
In
1.5
OutB
tD = 3.9386
1.0
0.5
0
2 4 6 8 10 12 14
TIME (nS)
Figure 12. Single versus Dual Waveforms
MPC972
OUTPUT
BUFFER
7Ω
RS = 36 Ω ZO = 50 Ω
RS = 36 Ω ZO = 50 Ω
7 Ω + 36 Ω k 36 Ω = 50 Ω k 50 Ω
25 Ω = 25 Ω
Figure 13. Optimized Dual Line Termination
SPICE level output buffer models are available for engineers
who want to simulate their specific interconnect schemes. In
addition IV characteristics are in the process of being
generated to support the other board level simulators in general
use.
Using the Output Freeze Circuitry
With the recent advent of a “green” classification for
computers the desire for unique power management among
MPC972
system designers is keen. The individual output enable control
of the MPC972 allows designers, under software control, to
implement unique power management schemes into their
designs. Although useful, individual output control at the
expense of one pin per output is too high, therefore a simple
serial interface was derived to economize on the control pins.
The freeze control logic provides a mechanism through
which the MPC972 clock outputs may be frozen (stopped in the
logic ‘0’ state):
The freeze mechanism allows serial loading of the 12–bit
Serial Input Register, this register contains one programmable
freeze enable bit for 12 of the 14 output clocks. The Qc0 and
QFB outputs cannot be frozen with the serial port, this avoids
any potential lock up situation should an error occur in the
loading of the Serial Input Register. The user may program an
output clock to freeze by writing logic ‘0’ to the respective freeze
enable bit. Likewise, the user may programmably unfreeze an
output clock by writing logic ‘1’ to the respective enable bit.
The freeze logic will never force a newly–frozen clock to a
logic ‘0’ state before the time at which it would normally
transition there. The logic simply keeps the frozen clock at logic
‘0’ once it is there. Likewise, the freeze logic will never force a
newly–unfrozen clock to a logic ‘1’ state before the time at which
it would normally transition there. The logic re–enables the
unfrozen clock during the time when the respective clock would
normally be in a logic ‘0’ state, eliminating the possibility of ‘runt’
clock pulses.
The user may write to the Serial Input register through the
Frz_Data input by supplying a logic ‘0’ start bit followed serially
by 12 NRZ freeze enable bits. The period of each Frz_Data bit
equals the period of the free–running Frz_Clk signal. The
Frz_Data serial transmission should be timed so the MPC972
can sample each Frz_Data bit with the rising edge of the
free–running Frz_Clk signal.
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 D11
D0-D3 are the control bits for Qa0-Qa3, respectively
D4-D7 are the control bits for Qb0-Qb3, respectively
D8-D10 are the control bits for Qc1-Qc3, respectively
D11 is the control bit for QSync
Figure 14. Freeze Data Input Protocol
MOTOROLA
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MPC972.PDF ] | |
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