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부품번호 MPC9774 기능
기능 LVCMOS PLL CLOCK GENERATOR
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MPC9774 데이터시트, 핀배열, 회로
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9774/D
Rev 1, 04/2002
Product Preview
3.3V/2.5V 1:14 LVCMOS PLL
Clock Generator
The MPC9774 is a 3.3V or 2.5V compatible, 1:14 PLL based clock
generator targeted for high performance low-skew clock distribution in
mid-range to high-performance networking, computing and telecom
applications. With output frequencies up to 125 MHz and output skews
less than 300 ps1 the device meets the needs of the most demanding
clock applications.
Features
1:14 PLL based low-voltage clock generator
2.5V or 3.3V power supply
Internal power–on reset
Generates clock signals up to 125 MHz
Maximum output skew of 300 ps1
Two LVCMOS PLL reference clock inputs
External PLL feedback supports zero-delay capability
Various feedback and output dividers (see application section)
Supports up to three individual generated output clock frequencies
Drives up to 28 clock lines
Ambient temperature range 0°C to +85°C
Pin and function compatible to the MPC974
MPC9774
3.3V/2.5V 1:14 LVCMOS
PLL CLOCK GENERATOR
FA SUFFIX
52 LEAD LQFP PACKAGE
CASE 848D
Functional Description
The MPC9774 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the
MPC9774 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The
reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match
the VCO frequency range.
The MPC9774 features frequency programmability between the three output banks outputs as well as the output to input
relationships. Output frequency ratios of 1:1, 2:1, 3:1, 3:2 and 3:2:1 can be realized. Additionally, the device supports a separate
configurable feedback output which allows for a wide variety of of input/output frequency multiplication alternatives. The
VCO_SEL pin provides an extended PLL input reference frequency range.
The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two
alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL
bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output
dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL
characteristics do not apply.
The MPC9774 has an internal power–on reset.
The MPC9774 is fully 2.5V and 3.3V compatible and requires no external loop filter components. All inputs (except XTAL)
accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50
transmission lines. For series terminated transmission lines, each of the MPC9774 outputs can drive one or two traces giving the
devices an effective fanout of 1:12. The device is pin and function compatible to the MPC974 and is packaged in a 52-lead LQFP
package.
1. Final specification of this parameter is pending characterization.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
© Motorola, Inc. 2002
1




MPC9774 pdf, 반도체, 판매, 대치품
MPC9774
Table 3. Function Table (Output Dividers Bank A, B, and C)
VCO_SEL FSEL_A
QA[4:0]
VCO_SEL FSEL_B
0 0 VCO ÷ 4 0 0
0 1 VCO ÷ 8 0 1
1 0 VCO ÷ 8 1 0
1 1 VCO ÷ 16 1 1
Table 4. Function Table (QFB)
VCO_SEL FSEL_B1 FSEL_B0
00
0
00
1
01
0
01
1
10
0
10
1
11
0
11
1
QFB
VCO ÷ 8
VCO ÷ 16
VCO ÷ 12
VCO ÷ 24
VCO ÷ 16
VCO ÷ 32
VCO ÷ 24
VCO ÷ 48
QB[4:0]
VCO ÷ 4
VCO ÷ 8
VCO ÷ 8
VCO ÷ 16
VCO_SEL
0
0
1
1
FSEL_C
0
1
0
1
QC[3:0]
VCO ÷ 8
VCO ÷ 12
VCO ÷ 16
VCO ÷ 24
MOTOROLA
4 TIMING SOLUTIONS

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MPC9774 전자부품, 판매, 대치품
MPC9774
Table 9. DC Characteristics (VCC = 2.5V ± 5%, TA = 0°C to + 85°C)
Symbol
Characteristics
Min
Typ
Max Unit
Condition
VCC_PLL PLL supply voltage
2.325
VCC
V LVCMOS
VIH Input high voltage
1.7
VCC + 0.3 V
LVCMOS
VIL
VOH
Input low voltage
Output High Voltage
-0.3 0.7 V LVCMOS
1.8 V IOH =-15 mAa
VOL
ZOUT
IIN
Output Low Voltage
Output impedance
Input Currentb
17 - 20
0.6
±200
V IOL = 15 mA
W
µA VIN = VCC or GND
ICC_PLL Maximum PLL Supply Current
2.0 5.0 mA VCCA Pin
ICC Maximum Quiescent Supply Current
1.0 mA All VCC Pins
a. The MPC9774 is capable of driving 50transmission lines on the incident edge. Each output drives one 50parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50series terminated transmission lines per
output.
b. Inputs have pull-down or pull-up resistors affecting the input current.
Table 10. AC Characteristics (VCC = 2.5V ± 5%, TA = 0°C to + 85°C)a b
Symbol
Characteristics
Min Typ Max Unit Condition
fref Input reference frequency
÷8 feedback
÷12 feedback
÷16 feedback
÷24 feedback
÷32 feedback
÷48 feedback
25.0
16.6
12.5
8.33
6.25
4.16
50.0 MHz PLL locked
33.3 MHz
25.0 MHz
16.6 MHz
12.5 MHz
8.3 MHz
fVCO
fMAX
Input reference frequency in PLL bypass modec
VCO frequency ranged
Output Frequency
÷4 output
÷8 output
÷12 output
÷16 output
÷24 output
200
50.0
25.0
16.6
12.5
8.33
TBD
400
100.0
50.0
33.3
25.0
16.6
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PLL bypass
PLL locked
frefDC
tr, tf
Reference Input Duty Cycle
CCLKx Input Rise/Fall Time
40 60 %
1 ns 0.7 to 1.7V
t() Propagation Delay (static phase offset)
CCLKx or PCLK to FB_IN
±150
ps PLL locked
tsk(O)
DC
Output-to-output Skewe
Output duty cycle
300 ps
45 50
55 %
tr, tf
tPLZ, HZ
tPZL, LZ
tJIT(CC)
tJIT(PER)
tJIT()
BW
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle-to-cycle jitter
Period Jitter
I/O Phase Jitter
PLL closed loop bandwidthg
0.1
RMS (1 σ)f
RMS (1 σ)
RMS (1 σ)
TBD
TBD
TBD
1.0
10
10
TBD
ns 0.6 to 1.8V
ns
ns
ps
ps
ps
kHz
tLOCK Maximum PLL Lock Time
10 ms
a. All AC characteristics are design targets and subject to change upon device characterization.
b. AC characteristics apply for parallel output termination of 50to VTT.
c. In bypass mode, the MPC9774 divides the input reference clock.
d. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fref = fVCO ÷ (M VCO_SEL).
e. See application section for part-to-part skew calculation.
f. See application section for a jitter calculation for other confidence factors than 1 σ.
g. -3 dB point of PLL transfer characteristics.
TIMING SOLUTIONS
7
MOTOROLA

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