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PDF MPC970 Data sheet ( Hoja de datos )
| Número de pieza | MPC970 | |
| Descripción | LOW VOLTAGE PLL CLOCK DRIVER | |
| Fabricantes | Motorola Semiconductors | |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Not Recommended for New Designs
See MPC972 or MPC974
Low Voltage PLL Clock Driver
MPC970
The MPC970 is a 3.3V compatible, PLL based clock driver devices
targeted for high performance RISC or CISC processor based systems.
• Fully Integrated PLL
• Output Frequency Up to 250MHz
• Compatible with PowerPC™ and Pentium™ Processors
• Output Frequency Configuration
• On–Board Crystal Oscillator
• 52–Lead TQFP Packaging
• ±50ps Typical Cycle–to–Cycle Jitter
LOW VOLTAGE
PLL CLOCK DRIVER
The MPC970 was designed specifically to drive today’s PowerPC 601
and Pentium processors while providing the necessary performance to
address higher frequency PowerPC 601 as well as PowerPC 603 and
PowerPC 604 applications. The 2x_PCLK output can toggle at up to
250MHz while the remaining outputs can be configured to drive the other
system clocks for MPC 601 based systems. As the processor based
clock speeds increase the processor bus will likely run at one third or
even one fourth the processor clock. The MPC970 supports the
necessary waveforms to drive the BCLKEN input signal of the MPC 601
when the processor bus is running at a lower frequency than the
FA SUFFIX
52–LEAD TQFP PACKAGE
CASE 848D–03
processor. The MPC970 uses an advanced PLL design which minimizes
the jitter generated on the outputs. The jitter specification is well within the
requirements of the Pentium processor and meets the stringent
preliminary specifications of the PowerPC 603 and PowerPC 604
processors. The application section of this data sheet deals in more detail
with driving PowerPC and Pentium processor based systems.
The external feedback option of the MPC970 provides for a near zero delay between the reference clock input and the outputs
of the device. This feature is required in applications where a master clock is being picked up off the backplane and regenerated
and distributed on a daughter card. The advanced PLL of the MPC970 eliminates the dead zone of the phase detector and
minimizes the jitter of the PLL so that the phase error variation is held to a minimum. This phase error uncertainty makes up a
major portion of the part–to–part skew of the device.
For single clock driver applications the MPC970 provides an internal oscillator and internal feedback to simplify board layout
and minimize system cost. By using the on–board crystal oscillator the MPC970 acts as both the clock generator and distribution
chip. The external component is a relatively inexpensive crystal rather than a more expensive oscillator. Since in single board
applications the delay between the input reference and the outputs is inconsequential an internal feedback option is offered. The
internal feedback simplifies board design in that the system designer need not worry about noise being coupled into the feedback
line due to board parasitics and layout. The internal feedback is a fixed divide by 32 of the VCO. This divide ratio ensures that the
input crystals will be ≤20MHz, thus keeping the crystal costs down and ensuring availability from multiple vendors.
PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.
1/97
© Motorola, Inc. 1997
1
REV 2
1 page  
MPC970
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Min Max Unit
VCC
Supply Voltage
–0.3 4.6 V
VI Input Voltage
–0.3
VDD + 0.3
V
IIN Input Current
±20 mA
TStor
Storage Temperature Range
–40 125 °C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is
not implied.
DC CHARACTERISTICS (TA = 0 to 70°C)
Symbol
Characteristic
Min Max Unit
Condition
VCC
Power Supply Voltage
3.0 3.8 V
ICC Quiescent Power Supply
250 mA
VIL Input Voltage LOW
LVCMOS Inputs
0.3VDD
V
VIH Input Voltage HIGH
LVCMOS Inputs 0.7VDD
V
IIH Input Current HIGH
LVCMOS Inputs
–100
µA VIN = VCC
IIL Input Current LOW
–200
µA VIN = GND
VOH
Output Voltage HIGH
VDD–0.2
V IOH = –20mA (Note 1.)
VOL
Output Voltage LOW
0.2 V IOL = 20mA (Note 1.)
IOZ Tristate Output Leakage Current
–10 10 µA VOH = VCC or GND
CIN Input Capacitance
4 pF
Cpd Power Dissipation Capacitance
pF
COUT
Output Capacitance
8 pF
1. The MPC970 outputs can drive series or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge (see Applications
Info section).
PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70°C)
Symbol
Characteristic
Min
tr, tf TCLK Input Rise/Falls
fref Reference Input Frequency
10
frefDC
Reference Input Duty Cycle
25
2. Maximum input reference is limited by the VCO lock range and the feedback divider.
Max
3.0
Note 2.
75
Unit
ns
MHz
%
Condition
TIMING SOLUTIONS
BR1333 — Rev 6
5
MOTOROLA
5 Page 
MPC970
Using the On–Board Crystal Oscillator
The MPC970 features an on–board crystal oscillator to
allow for seed clock generaytion as well as final distribution.
The on–board oscillator is completely self contained so that
the only external component required is the crystal. As the
oscillator is somewhat sensitive to loading on its inputs the
user is advised to mount the crystal as close to the MPC970
as possible to avoid any board level parasitics. To facilitate
co–location surface mount crystals are recommended, but
not required. In addition, with crystals with a higher shunt
capacitance, it may be necessary to place a 1k resistor
across the two crystal leads.
The oscillator circuit is a series resonant circuit as
opposed to the more common parallel resonant circuit, this
eliminates the need for large on–board capacitors. Because
the design is a series resonant design for the optimum
frequency accuracy a series resonant crystal should be used
(see specification table below). Unfortunately most off the
shelf crystals are characterized in a parallel resonant mode.
However a parallel resonant crystal is physically no different
than a series resonant crystal, a parallel resonant crystal is
simply a crystal which has been characterized in its parallel
resonant mode. Therefore in the majority of cases a parallel
specified crystal can be used with the MPC970 with just a
minor frequency error due to the actual series resonant
frequency of the parallel resonant specified crystal. Typically
a parallel specified crystal used in a series resonant mode
will exhibit an oscillatory frequency a few hundred ppm lower
than the specified value. For most processor
implementations a few hundred ppm translates into kHz
inaccuracies, a level which does not represent a major issue.
Table 3. Crystal Specifications
Parameter
Value
Crystal Cut
Fundamental at Cut
Resonance
Series Resonance*
Frequency Tolerance
±75ppm at 25°C
Frequency/Temperature Stability
±150pm 0 to 70°C
Operating Range
0 to 70°C
Shunt Capacitance
5–7pF
Equivalent Series Resistance (ESR) 50 to 80Ω
Correlation Drive Level
100µW
Aging
5ppm/Yr (First 3 Years)
* See accompanying text for series versus parallel resonant
discussion.
The MPC970 is a clock driver which was designed to
generate outputs with programmable frequency relationships
and not a synthesizer with a fixed input frequency. As a result
the crystal input frequency is a function of the desired output
frequency. For a design which utilizes the external feedback
to the PLL the selection of the crystal frequency is straight
forward; simply chose a crystal which is equal in frequency to
the fed back signal. To determine the crystal required to
produce the desired output frequency for an application
which utilizes internal feedback the block diagram of Figure 8
should be used. The P and the M values for the MPC970 are
also included in Figure 8. The M values can be found in the
configuration tables included in this applications section.
fref VCO
Phase
Detector LPF
÷P ÷N Qn
÷m
+ +fref
fVCO
m
,
fVCO
fQn · N · P
N +fref
fQn · N · P
m
m = 32
P = 1 (VCO_Sel=‘1’), 2(VCO_Sel=‘0’)
Figure 8. PLL Block Diagram
For the MPC970 clock driver, the following will provide an
example of how to determine the crystal frequency required
for a given design.
Given:
2x_PCLK = 200MHz
PCLKEN = 100MHz
BCLK
= 50MHz
PCI_CLK = 25MHz
VCO_SEL = ‘1’
+fref
fQn · N · P
m
From Table 3
PCI_CLK = VCO/16 then N = 16
or
PCLKEN = VCO/4 then N = 4
From Figure 8
m = 32 and P = 1
+ + +fref
25 · 16 · 1
32
12.5MHz or 100 · 4 · 1
32
12.5MHz
Driving Transmission Lines
The MPC970 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 10Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091 in the
Timing Solutions brochure (BR1333/D).
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a
point–to–point scheme either series terminated or parallel
TIMING SOLUTIONS
BR1333 — Rev 6
11
MOTOROLA
11 Page | ||
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| PDF Descargar | [ Datasheet MPC970.PDF ] | |
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