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PDF ATMLH412 Data sheet ( Hoja de datos )
| Número de pieza | ATMLH412 | |
| Descripción | Two-wire Serial EEPROM | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Low-voltage and Standard-voltage Operation
⎯ 1.8 (V = 1.8V to 5.5V)
CC
• Internally Organized as 32,768 x 8
• Two-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 1 MHz (5.0V, 2.7V, 2.5V), and 400 kHz (1.8V) Compatibility
• Write Protect Pin for Hardware and Software Data Protection
• 64-byte Page Write Mode (Partial Page Writes Allowed)
• Self-timed Write Cycle (5 ms Max)
• High Reliability
⎯ Endurance: One Million Write Cycles
⎯ Data Retention: 40 Years
• Lead-free/Halogen-free Devices Available
• 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, EIAJ SOIC, 8-lead Ultra Thin Small
Array Package (SAP), 8-lead TSSOP, and 8-ball dBGA2 Packages
• Die Sales: Wafer Form, Waffle Pack and Bumped Wafers
Description
The ATMLH412 provides 262,144 bits of serial electrically erasable and
programmable read-only memory (EEPROM) organized as 32,768 words of 8 bits
each. The device’s cascadable feature allows up to eight devices to share a common
two-wire bus. The device is optimized for use in many industrial and commercial
applications where low-power and low-voltage operation are essential. The devices
are available in space-saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra
Thin SAP, 8-lead TSSOP, and 8-ball dBGA2 packages. In addition, the entire family is
available in a 1.8V (1.8V to 5.5V) version.
Table 1. Pin Configurations
Pin Name
A0 – A2
SDA
SCL
Function
Address Inputs
Serial Data
Serial Clock Input
WP Write Protect
GND
Ground
8-lead PDIP
A0 1
A1 2
8 VCC
7 WP
A2 3
6 SCL
GND 4
5 SDA
A0
A1
A2
GND
8-lead SOIC
18
27
36
45
VCC
WP
SCL
SDA
8-ball dBGA2
VCC 8
WP 7
1 A0
2 A1
SCL 6 3 A2
SDA 5 4 GND
Bottom View
8-lead TSSOP
A0 1
A1 2
8 VCC
7 WP
A2 3
6 SCL
GND 4
5 SDA
8-lead Ultra-Thin SAP
VCC 8
1 A0
WP 7 2 A1
SCL 6 3 A2
SDA 5 4 GND
Bottom View
Two-wire
Serial EEPROM
256K (32,768 x 8)
ATMLH412
8568A–SEEPR–11/08
1 page  
Table 4. AC Characteristics (Industrial Temperature)
Applicable over recommended operating range from:
TAI = − 40°C to +85°C, VCC = +1.8V to +5.5V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note 2.
Symbol
Parameter
1.8-volt
Min Max
2.5, 5.0-volt
Min Max
Units
fSCL
tLOW
tHIGH
tI
tAA
tBUF
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
tF
tSU.STO
tDH
tWR
Endurance(1)
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time(1)
Clock Low to Data Out Valid
Time the bus must be free before a new transmission can start(1)
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time(1)
Inputs Fall Time(1)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
25°C, Page Mode, 3.3V
1.3
0.6
0.05
1.3
0.6
0.6
0
100
0.6
50
400
0.4
0.4
100
0.9 0.05
0.5
.25
0.25
0
100
0.3
300
0.25
50
5
1,000,000
1000
50
0.55
0.3
100
5
kHz
μs
μs
ns
μs
μs
μs
μs
μs
ns
μs
ns
μs
ns
ms
Write
Cycles
Note:
1. This parameter is ensured by characterization and is not 100% tested.
2. AC measurement conditions:
R (connects to V ): 1.3 kΩ (2.5V, 5.5V), 10 kΩ (1.8V)
L CC
Input pulse voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: ≤ 50 ns
Input and output timing reference voltages: 0.5 VCC
8568A–SEEPR–11/08
5 Page 
6. Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write select bit in the
device address word is set to “1”. There are three read operations: current address read, random address read, and
sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the
last read or write operation, incremented by one. This address stays valid between operations as long as the chip
power is maintained. The address “roll over” during read is from the last byte of the last memory page, to the first byte
of the first page.
Once the device address with the read/write select bit set to “1” is clocked in and acknowledged by the EEPROM, the
current address data word is serially clocked out. The microcontroller does not respond with an input “0” but does
generate a following stop condition (refer to Figure 11).
Figure 11. Current Address Read
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the
device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller
must generate another start condition. The microcontroller now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the
data word. The microcontroller does not respond with a “0” but does generate a following stop condition. (Refer to
Figure 12)
Figure 12. Random Read
Note: * = DON’T CARE bit
8568A–SEEPR–11/08
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ATMLH412.PDF ] | |
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