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A3P125 데이터시트 PDF




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기능 ProASIC3 Flash Family FPGAs
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A3P125 데이터시트, 핀배열, 회로
Revision 13
ProASIC3 Flash Family FPGAs
with Optional Soft ARM Support
Features and Benefits
High Capacity
• 15 k to 1 M System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
• Instant On Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI
In-System Programming (ISP) and Security
• ISP Using On-Chip 128-Bit Advanced Encryption Standard
(AES) Decryption (except ARM®-enabled ProASIC®3 devices)
via JTAG (IEEE 1532–compliant)
• FlashLock® to Secure FPGA Contents
Low Power
• Core Voltage for Low Power
• Support for 1.5 V-Only Systems
• Low-Impedance Flash Switches
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
Single-Ended
2.5 V / 1.8 V /
I/O
1.5 V,
Standards:
3.3 V PCI /
3L.V3TVTLP, CI-LXVCManOdSLVC3.M3 OVS/
2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS (A3P250 and above)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os
• Programmable Output Slew Rateand Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase-Shift, Multiply/Divide, Delay Capabilities
and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
• True Dual-Port SRAM (except ×18)
ARM Processor Support in ProASIC3 FPGAs
• M1 ProASIC3 Devices—ARM®Cortex™-M1 Soft Processor
Available with or without Debug
ProASIC3 Devices
Cortex-M1 Devices 2
A3P0151 A3P030
A3P060 A3P125 A3P250
A3P400
A3P600
A3P1000
M1A3P250 M1A3P400 M1A3P600 M1A3P1000
System Gates
15,000
30,000
60,000 125,000 250,000
400,000
600,000
1,000,000
Typical Equivalent Macrocells 128
256
512 1,024
2,048
VersaTiles (D-flip-flops)
384
768
1,536 3,072
6,144
9,216
13,824
24,576
RAM Kbits (1,024 bits)
18 36
36
54 108 144
4,608-Bit Blocks
48
8
12 24
32
FlashROM Kbits
Secure (AES) ISP 3
11
11
1
1
1
1
Yes Yes
Yes
Yes
Yes
Yes
Integrated PLL in CCCs
11
1
1
1
1
VersaNet Globals 4
6
6
18 18
18
18
18
18
I/O Banks
22
22
4
4
4
4
Maximum User I/Os
49
81
96 133
157
194
235
300
Package Pins
QFN
CS
VQFP
TQFP
PQFP
FBGA
QN68
QN48, QN68,
QN132
VQ100
QN132
CS121
VQ100
TQ144
FG144
QN132 QN132 5
VQ100
TQ144
PQ208
FG144
VQ100
PQ208
FG144/256
5
PQ208
FG144/256/
484
PQ208
FG144/256/
484
PQ208
FG144/256/
484
Notes:
1. A3P015 is not recommended for new designs.
2. Refer to the Cortex-M1 product brief for more information.
3. AES is not available for Cortex-M1 ProASIC3 devices.
4. Six chip (main) and three quadrant global networks are available for A3P060 and above.
5. The M1A3P250 device does not support this package.
6. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs datasheet.
† A3P015 and A3P030 devices do not support this feature.
January 2013
© 2013 Microsemi Corporation
‡ Supported only by A3P015 and A3P030 devices.
I




A3P125 pdf, 반도체, 판매, 대치품
ProASIC3 Flash Family FPGAs
Temperature Grade Offerings
Package
A3P015* A3P030 A3P060 A3P125
A3P250
Cortex-M1 Devices
M1A3P250
QN48
– C, I –
QN68
C, I C, I
QN132
– C, I C, I C, I
C, I
CS121
– – C, I –
VQ100
– C, I C, I C, I
C, I
TQ144
– – C, I C, I
PQ208
– – – C, I C, I
FG144
– – C, I C, I C, I
FG256
––––
C, I
FG484
––––
Note: *A3P015 is not recommended for new designs.
C = Commercial temperature range: 0°C to 70°C ambient temperature
I = Industrial temperature range: –40°C to 85°C ambient temperature
A3P400
M1A3P400
C, I
C, I
C, I
C, I
A3P600
M1A3P600
C, I
C, I
C, I
C, I
A3P1000
M1A3P1000
C, I
C, I
C, I
C, I
Speed Grade and Temperature Grade Matrix
Temperature Grade
C1
Std.
I2
Notes:
1. C = Commercial temperature range: 0°C to 70°C ambient temperature
2. I = Industrial temperature range: –40°C to 85°C ambient temperature
–1
–2
References made to ProASIC3 devices also apply to ARM-enabled ProASIC3 devices. The ARM-enabled part numbers start with
M1 (Cortex-M1).
Contact your local Microsemi representative for device availability: http://www.microsemi.com/soc/contact/default.aspx.
A3P015 and A3P030
The A3P015 and A3P030 are architecturally compatible; there are no RAM or PLL features.
Devices Not Recommended For New Designs
A3P015 is not recommended for new designs.
IV Revision 13

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A3P125 전자부품, 판매, 대치품
1 – ProASIC3 Device Family Overview
General Description
ProASIC3, the third-generation family of Microsemi flash FPGAs, offers performance, density, and
features beyond those of the ProASICPLUS® family. Nonvolatile flash technology gives ProASIC3 devices
the advantage of being a secure, low power, single-chip solution that is Instant On. ProASIC3 is
reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable
designers to create high-density systems using existing ASIC or FPGA design flows and tools.
ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as
clock conditioning circuitry based on an integrated phase-locked loop (PLL). The A3P015 and A3P030
devices have no PLL or RAM support. ProASIC3 devices have up to 1 million system gates, supported
with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os.
ProASIC3 devices support the ARM Cortex-M1 processor. The ARM-enabled devices have Microsemi
ordering numbers that begin with M1A3P (Cortex-M1) and do not support AES decryption.
Flash Advantages
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-
based FPGAs, flash-based ProASIC3 devices allow all functionality to be Instant On; no external boot
PROM is required. On-board security mechanisms prevent access to all the programming information
and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system
reprogramming to support future design iterations and field upgrades with confidence that valuable
intellectual property (IP) cannot be compromised or copied. Secure ISP can be performed using the
industry-standard AES algorithm. The ProASIC3 family device architecture mitigates the need for ASIC
migration at higher user volumes. This makes the ProASIC3 family a cost-effective ASIC replacement
solution, especially for applications in the consumer, networking/ communications, computing, and
avionics markets.
Security
The nonvolatile, flash-based ProASIC3 devices do not require a boot PROM, so there is no vulnerable
external bitstream that can be easily copied. ProASIC3 devices incorporate FlashLock, which provides a
unique combination of reprogrammability and design security without external overhead, advantages that
only an FPGA with nonvolatile flash programming can offer.
ProASIC3 devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest level
of protection in the FPGA industry for intellectual property and configuration data. In addition, all
FlashROM data in ProASIC3 devices can be encrypted prior to loading, using the industry-leading
AES-128 (FIPS192) bit block cipher encryption standard. The AES standard was adopted by the National
Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3
devices have a built-in AES decryption engine and a flash-based AES key that make them the most
comprehensive programmable logic device security solution available today. ProASIC3 devices with
AES-based security provide a high level of protection for remote field updates over public networks such
as the Internet, and are designed to ensure that valuable IP remains out of the hands of system
overbuilders, system cloners, and IP thieves.
ARM-enabled ProASIC3 devices do not support user-controlled AES security mechanisms. Since the
ARM core must be protected at all times, AES encryption is always on for the core logic, so bitstreams
are always encrypted. There is no user access to encryption for the FlashROM programming data.
Security, built into the FPGA fabric, is an inherent component of the ProASIC3 family. The flash cells are
located beneath seven metal layers, and many device design and layout techniques have been used to
make invasive attacks extremely difficult. The ProASIC3 family, with FlashLock and AES security, is
unique in being highly resistant to both invasive and noninvasive attacks.
Revision 13
1-1

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