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부품번호 | W79L633A 기능 |
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기능 | 8-BIT MICROCONTROLLER | ||
제조업체 | nuvoton | ||
로고 | |||
전체 30 페이지수
W79E633A/W79L633A DATA SHEET
8-BIT MICROCONTROLLER
Table of Contents-
1. GENERAL DESCRIPTION ......................................................................................................... 4
2. FEATURES ................................................................................................................................. 4
3. PIN CONFIGURATION ............................................................................................................... 6
4. PIN DESCRIPTION..................................................................................................................... 7
4.1 Port 4 .............................................................................................................................. 8
5. MEMORY ORGANIZATION...................................................................................................... 10
5.1 Program Memory (on-chip Flash) ................................................................................. 10
5.2 Data Memory ................................................................................................................ 11
6. SPECIAL FUNCTION REGISTERS ......................................................................................... 12
7. INSTRUCTION SET.................................................................................................................. 42
7.1 Instruction Timing.......................................................................................................... 50
7.1.1 External Data Memory Access Timing............................................................................52
8. POWER MANAGEMENT.......................................................................................................... 55
8.1 Idle Mode ...................................................................................................................... 55
8.2 Power Down Mode ....................................................................................................... 55
9. RESET ...................................................................................................................................... 56
9.1 Reset Conditions........................................................................................................... 56
9.2 External Reset .............................................................................................................. 56
9.3 Power-On Reset (POR) ................................................................................................ 56
9.4 Watchdog Timer Reset ................................................................................................. 56
9.5 Reset State ................................................................................................................... 56
10. INTERRUPTS ........................................................................................................................... 58
10.1 Interrupt Sources .......................................................................................................... 58
10.2 Priority Level Structure ................................................................................................. 59
11. PROGRAMMABLE TIMERS/COUNTERS ............................................................................... 60
11.1 Timer/Counters 0 & 1.................................................................................................... 60
11.1.1 Time-Base Selection ....................................................................................................60
11.1.2 Mode 0 .........................................................................................................................60
11.1.3 Mode 1 .........................................................................................................................61
11.1.4 Mode 2 .........................................................................................................................61
11.1.5 Mode 3 .........................................................................................................................62
11.2 Timer/Counter 2 ............................................................................................................ 62
11.2.1 Capture Mode...............................................................................................................63
11.2.2 Auto-reload Mode, Counting up....................................................................................63
11.2.3 Auto-reload Mode, Counting Up/Down .........................................................................64
11.2.4 Baud Rate Generator Mode .........................................................................................65
12. WATCHDOG TIMER................................................................................................................. 66
13. PULSE-WIDTH-MODULATED (PWM) OUTPUTS ................................................................... 69
Publication Release Date: Oct 08, 2010
- 1 - Revision A6.0
W79E633A/W79L633A
1. General Description
The W79E(L)633 is a fast, 8051/52-compatible microcontroller with a redesigned processor core that
eliminates wasted clock and memory cycles. Typically, the W79E(L)633 executes instructions 1.5 to 3
times faster than that of the traditional 8051/52, depending on the type of instruction, and the overall
performance is about 2.5 times better at the same crystal speed. As a result, with the fully-static
CMOS design, the W79E(L)633 can accomplish the same throughput with a lower clock speed,
reducing power consumption.
The W79E(L)633 provides 256 bytes of on-chip RAM; 1-KB of auxiliary RAM; four 8-bit, bi-directional
and bit-addressable I/O ports; an additional 4-bit port P4; three 16-bit timer/counters; an UART serial
port, 2 channels of I2C with master/slave capability and 4 channels of 10-bit ADC. These peripherals
are all supported by ten interrupt sources with 2 levels of priority.
The W79E(L)633 contains a 128-KB Flash EPROM whose contents may be updated in-system by a
loader program stored in an auxiliary, 4-KB Flash EPROM. Once the contents are confirmed, it can be
protected for security.
Note: If the applied VDD is not stable, especially with long transition time of power on/off, it’s
recommended to apply an external RESET IC to the RST pin for improving the stability of
system.
2. Features
• Fully-static-design 8-bit Turbo 51 CMOS microcontroller up to 40MHz
• 128-KB of in-system-programmable Flash EPROM (AP Flash EPROM)
• 4-KB of Auxiliary Flash EPROM for the loader program (LD Flash EPROM)
• 1-KB auxiliary RAM, software-selectable, accessed by MOVX instruction
• 256 bytes of scratch-pad RAM
• Four 8-bit bi-directional ports
• All pins with Schmitt trigger inputs
• One 4-bit multipurpose I/O port4 with Chips select(CS) and boot function
• Three 16-bit timers
• 6 channel of 8-bit PWM
• One enhanced full-duplex UART with framing-error detection and automatic address recognition
• 2-channels of I2C with master/slave capability
• 10-bit ADC with 4-channel inputs
• Software programmable access cycle to external RAM/peripherals
• 10 interrupt sources with two levels of priority
• Software reset function
• Optional H/L state of ALE/PSEN during power down mode
• Built-in power management
• Code protection
• Development tool
— JTAG ICE(In Circuit Emulator) tool
• Packages:
— Lead Free(RoHS) PLCC 44:
— Lead Free(RoHS) QFP 44:
W79E633A40PL, W79L633A25PL
W79E633A40FL, W79L633A25FL
-4-
4페이지 W79E633A/W79L633A
4. Pin Description
SYMBOL
EA
TYPE
I
DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute
the external ROM. The ROM address and data are not presented on the bus
if the EA pin is high.
PSEN
ALE
RST
XTAL1
XTAL2
VSS
VDD
P0.0−P0.7
P1.0−P1.7
P2.0−P2.7
OH
OH
IL
I
O
I
I
I/O
DSH
I/O
SH
I/O
SH
PROGRAM STORE ENABLE: PSEN enables the external ROM data in the
Port 0 address/data bus. When internal ROM access is performed, no PSEN
strobe signal outputs originate from this pin.
ADDRESS LATCH ENABLE: ALE enables the address latch that separates
the address from the data on Port 0.
RESET: Set this pin high for two machine cycles while the oscillator is
running to reset the device.
CRYSTAL 1: Crystal oscillator input or external clock input.
CRYSTAL 2: Crystal oscillator output.
GROUND: ground potential.
POWER SUPPLY: Supply voltage for operation.
PORT 0: 8-bit, bi-directional I/O port with internal pull-up resisters. This port
also provides a multiplexed, low-order address / data bus during accesses to
external memory.
PORT 1: 8-bit, bi-directional I/O port with internal pull-up resistors. This port
also provides alternate functions as below.
P1.0 ~ P1.5 provide PWM0 ~ PWM5.
P1.4 ~ P1.7 provide ADC0 ~ ADC3.
P1.0 alternately provides Timer2 external count input.(T2)
P1.1 alternately provides Timer2 Reload/Capture/Direction control.(T2Ex)
PORT 2: 8-bit, bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits when accessing external memory. P2.4 to
P2.7 can be software configured as I2C serial ports
PORT 3: 8-bit, bi-directional I/O port with internal pull-up resistors.
All bits have alternate functions, which are described below:
RXD (P3.0): Serial Port 0 input
TXD (P3.1): Serial Port 0 output
P3.0−P3.7
I/O
SH
INT0 (P3.2): External Interrupt 0
INT1(P3.3): External Interrupt 1
T0 (P3.4):Timer 0 External Input
T1 (P3.5):Timer 1 External Input
WR (P3.6): External Data Memory Write Strobe
P4.0−P4.3
I/O
SH
RD (P3.7): External Data Memory Read Strobe
PORT 4: 4-bit bi-directional I/O port. The P4.3 also provides the alternate
function REBOOT which is H/W reboot from LD flash.
* Note : TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain S: Schmitt Trigger
Publication Release Date: Oct 07, 2010
- 7 - Revision A6.0
7페이지 | |||
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