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PDF EM78156E Data sheet ( Hoja de datos )
| Número de pieza | EM78156E | |
| Descripción | 8-Bit Microcontroller | |
| Fabricantes | ELAN Microelectronics | |
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EM78156E
8-Bit Microcontroller
with MASK ROM
Product
Specification
DOC. VERSION 1.4
ELAN MICROELECTRONICS CORP.
April 2016
1 page  
Contents
1 General Description
EM78156E is an 8-bit microprocessor with low-power and high-speed CMOS
technology. Integrated into a single chip are on-chip Watchdog Timer (WDT), RAM,
ROM, real time clock/counter, external and internal interrupt, power down mode, and
tri-state I/O.
2 Features
Operating voltage range : 2.3V~5.5V
Operating temperature range: 0C~70C
Operating frequency rang (base on 2 clocks ):
Crystal mode: DC~20 MHz at 5V, DC~8 MHz at 3V, DC~4 MHz at 2.3V.
ERC mode: DC~4 MHz at 5V, DC~4 MHz at 3V, DC~4 MHz at 2.3V.
Low power consumption:
Less then 2.0 mA at 5V/4 MHz
Typically 15 A at 3V/32kHz
Typically 1 A during sleep mode
1K 13 bits on chip ROM
One configuration register to accommodate user’s requirements
48 8 bits on chip registers (SRAM, general purpose register)
2 bi-directional I/O ports
5 level stacks for subroutine nesting
8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and
overflow interrupt
Two clocks per instruction cycle
Power down (SLEEP) mode
Three available interruptions
TCC overflow interrupt
Input-port status changed interrupt (wake up from sleep mode)
External interrupt
Programmable free running Watchdog Timer
8 programmable pull-high pins
7 programmable pull-down pins
8 programmable open-drain pins
2 programmable R-option pins
Product Specification (V1.4) 04.27.2016
(This specification is subject to change without prior notice)
1
5 Page 
EM78156E
8-Bit Microcontroller with MASK ROM
Bit 4 (T) Time-out bit.
Set to 1 with the "SLEP" and "WDTC" commands, or during power up and
reset to 0 by WDT time-out.
Bits 5 ~7 (GP0 ~ 2) General purpose read/write bits.
4.1.5 R4 (RAM Select Register)
Bits 0~5 are used to select registers (address: 00~06, 0F~3F) in the indirect
addressing mode.
Bits 6~7 are not used (read only).
Bits 6~7 are set to “1” at all time.
Z flag of R3 will set to “1”, when R4 content is equal to “3F” When R4=R4+1,
R4 content will select as R0.
See the configuration of the data memory in Fig. 4.
4.1.6 R5 ~ R6 (Port 5 ~ Port 6)
R5 and R6 are I/O registers.
Only the lower 4 bits of R5 are available.
4.1.7 RF (Interrupt Status Register)
76543210
- - - - - EXIF ICIF TCIF
“1” means with interrupt request, and “0” means no interrupt occur.
Bit 0 (TCIF) TCC overflow interrupt flag. Set when TCC overflows, reset by software.
Bit 1 (ICIF) Port 6 input status change interrupt flag. Set when Port 6 input changes,
reset by software.
Bit 2 (EXIF) External interrupt flag. Set by falling edge on /INT pin, reset by software.
Bits 3 ~ 7 Not used.
RF can be cleared by instruction but cannot be set.
IOCF is the interrupt mask register.
Note that the result of reading RF is the "logic AND" of RF and IOCF.
4.1.8 R10 ~ R3F
All of these are 8-bit general-purpose registers.
Product Specification (V1.4) 04.27.2016
(This specification is subject to change without prior notice)
7
11 Page | ||
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