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PDF K6F4008U2G-F Data sheet ( Hoja de datos )
| Número de pieza | K6F4008U2G-F | |
| Descripción | 512K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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K6F4008U2G Family
Preliminary
CMOS SRAM
Document Title
512K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No. History
0.0 Initial Draft
Draft Date
June 11, 2003
Remark
Preliminary
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
- 1 - Revision 0.0
June 2003
1 page  
K6F4008U2G Family
Preliminary
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See right): CL= 100pF+1TTL
CL=30pF+1TTL
VTM3)
R12)
CL1)
R22)
1. Including scope and jig capacitance
2. R1=3070Ω, R2=3150Ω
3. VTM =2.8V
AC CHARACTERISTICS(Vcc=2.7~3.3V, Industrial product:TA=-40 to 85°C)
Parameter List
Symbol
Read
Write
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Chip Select to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
tRC
tAA
tCO
tOE
tLZ
tOLZ
tHZ
tOHZ
tOH
tWC
tCW
tAS
tAW
tWP
tWR
tWHZ
tDW
tDH
tOW
Speed
55ns
70ns
Min Max Min Max
55 - 70 -
- 55 - 70
- 55 - 70
- 25 - 35
10 - 10 -
5-5-
0 20 0 25
0 20 0 25
10 - 10 -
55 - 70 -
45 - 60 -
0-0-
45 - 60 -
40 - 50 -
0-0-
0 20 0 20
25 - 30 -
0-0-
5-5-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Min Typ Max Unit
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
VDR
IDR
tSDR
tRDR
CS1≥Vcc-0.2V1)
Vcc=1.5V, CS1≥Vcc-0.2V1), VIN≥0V
See data retention waveform
1.5
-
0
tRC
-
-
-
-
3.3 V
3 µA
- ns
-
1. CS1≥Vcc-0.2V, CS2≥Vcc-0.2V(CS1 controlled) or 0≤CS2≤0.2V(CS2 controlled).
- 5 - Revision 0.0
June 2003
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet K6F4008U2G-F.PDF ] | |
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