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PDF K6F4008U2E Data sheet ( Hoja de datos )
| Número de pieza | K6F4008U2E | |
| Descripción | 512K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM | |
| Fabricantes | Samsung semiconductor | |
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K6F4008U2E Family
CMOS SRAM
Document Title
512K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No. History
0.0 Initial Draft
1.0 Finalize
Draft Date
Remark
October 25, 2000 Preliminary
March 12, 2001 Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
- 1 - Revision 1.0
March 2001
1 page  
K6F4008U2E Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load (See right): CL= 100pF+1TTL
CL=30pF+1TTL
VTM3)
R12)
CL1)
R22)
1. Including scope and jig capacitance
2. R1=3070Ω, R2=3150Ω
3. VTM =2.8V
AC CHARACTERISTICS(Vcc=2.7~3.3V, Industrial product:TA=-40 to 85°C)
Parameter List
Read
Write
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Chip Select to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Symbol
tRC
tAA
tCO
tOE
tLZ
tOLZ
tHZ
tOHZ
tOH
tWC
tCW
tAS
tAW
tWP
tWR
tWHZ
tDW
tDH
tOW
Speed Bins
55ns
70ns
Min Max Min Max
55 - 70 -
- 55 - 70
- 55 - 70
- 25 - 35
10 - 10 -
5-5-
0 20 0 25
0 20 0 25
10 - 10 -
55 - 70 -
45 - 60 -
0-0-
45 - 60 -
40 - 50 -
0-0-
0 20 0 20
25 - 30 -
0-0-
5-5-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Vcc for data retention
VDR
CS1≥Vcc-0.2V1)
Data retention current
IDR Vcc=1.5V, CS1≥Vcc-0.2V1), VIN≥0V
Data retention set-up time
Recovery time
tSDR
tRDR
See data retention waveform
1. CS1≥Vcc-0.2V, CS2≥Vcc-0.2V(CS1 controlled) or 0≤CS2≤0.2V(CS2 controlled).
2. Typical value are measured at TA=25°C and not 100% tested.
Min
1.5
-
0
tRC
Typ
-
0.52)
-
-
Max
3.3
3
-
-
Unit
V
µA
ns
- 5 - Revision 1.0
March 2001
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet K6F4008U2E.PDF ] | |
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