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H0500KC25V PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 H0500KC25V
기능 Fast Symmetrical Gate Turn-Off Thyristor
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H0500KC25V 데이터시트, 핀배열, 회로
WESTCODE
An IXYS Company
Date:- 4 Aug, 2004
Data Sheet Issue:- 2
Fast Symmetrical Gate Turn-Off Thyristor
Type H0500KC25#
Absolute Maximum Ratings
VDRM
VRSM
VRRM
VRSM
VOLTAGE RATINGS
Repetitive peak off-state voltage, (note 1)
Non-repetitive peak off-state voltage, (note 1)
Repetitive peak reverse voltage
Non-repetitive peak reverse voltage
MAXIMUM
LIMITS
2500
2600
100-2000
100-2000
UNITS
V
V
V
V
ITGQM
Ls
IT(AV)M
IT(RMS)
ITSM
ITSM2
I2t
di/dtcr
PFGM
PRGM
IFGM
VRGM
toff
ton
Tjop
Tstg
RATINGS
Maximum peak turn-off current, (note 2)
Snubber loop inductance, ITM=ITGQM, (note 2)
Mean on-state current, Tsink=55°C (note 3)
Nominal RMS on-state current, 25°C (note 3)
Peak non-repetitive surge current tp=10ms
Peak non-repetitive surge current, (Note 4)
I2t capacity for fusing tp=10ms
Critical rate of rise of on-state current, (note 5)
Peak forward gate power
Peak reverse gate power
Peak forward gate current
Peak reverse gate voltage (note 6)
Minimum permissible off-time, ITM=ITGQM, (note 2)
Minimum permissible on-time
Operating temperature range
Storage temperature range
Notes:-
1) VGK=-2Volts.
2) Tj=125°C, VD=80%VDM, VDM<VDRM, diGQ/dt=20A/µs, CS=3µF.
3) Double-side cooled, single phase; 50Hz, 180° half-sinewave.
4) Half-sinewave, tp=2ms
5) For di/dt>1000A/µs, consult factory.
6) May exceed this value during turn-off avalanche period.
MAXIMUM
LIMITS
500
0.3
540
280
3.0
5.4
45
1000
160
5
100
18
60
10
-40 to +125
-40 to +150
UNITS
A
µH
A
A
kA
kA
kA2s
A/µs
W
kW
A
V
µs
µs
°C
°C
Data Sheet. Type H0500KC25# Issue 2
Page 1 of 15
August, 2004




H0500KC25V pdf, 반도체, 판매, 대치품
WESTCODE An IXYS Company
Fast Symmetrical Gate Turn-Off Thyristor type H0500KC25#
1.7 Critical rate of rise of on-state current
The value given is the maximum repetitive rating, but does not imply any specific operating condition. The
high turn-on losses associated with limit di/dt would not allow for practical duty cycle at this maximum
condition. For special pulse applications, such as crowbars and pulse power supplies, a much higher di/dt
is possible. Where the device is required to operate with infrequent high current pulses, with natural
commutation (i.e. not gate turn-off), then di/dt>5kA/µs is possible. For this type of operation individual
specific evaluation is required.
1.8 Gate ratings
The absolute conditions above which the gate may be damaged. It is permitted to allow VGK(AV) during turn-
off (see diagram 10) to exceed VRGM which is the implied DC condition.
1.9 Minimum permissible off time.
This time relates specifically to re-firing of device (see also note on gate-off time 2.7). The value given in
the ratings applies only to operating conditions of ratings note 2. For other operating conditions see the
curves of figure 18.
1.10 Minimum permissible on-time.
Figure is given for minimum time to allow complete conduction of all the GTO thyristor islands. Where a
simple snubber, of the form given in diagram 1. (or any other non-energy recovery type which discharges
through the GTO at turn-on) the actual minimum on-time will usually be fixed by the snubber circuit time
constant, which must be allowed to fully discharge before the GTO thyristor is turned off. If the anode
circuit has di/dt<10A/µs then the minimum on-time should be increased, the actual value will depend upon
the di/dt and operating conditions (each case needs to be assessed on an individual basis).
Data Sheet. Type H0500KC25# Issue 2
Page 4 of 15
August, 2004

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H0500KC25V 전자부품, 판매, 대치품
WESTCODE An IXYS Company
Fast Symmetrical Gate Turn-Off Thyristor type H0500KC25#
In addition to the turn-on time figures given in the characteristics data, the curves of figure 9 give the
relationship of tgt to di/dt and IGM. The data in the curves of figures 7 & 8, gives the turn-on losses both with
and without snubber discharge, a snubber of the form given in diagram 2 is assumed. Only typical losses
are given due to the large number of variables which effect Eon. It is unlikely that all negative aspects
would appear in any one application, so typical figures can be considered as worst case. Where the turn-
on loss is higher than the figure given it will in most cases be compensated by reduced turn-off losses, as
variations in processing inversely effect many parameters. For a worst case device, which would also
have the lowest turn-off losses, Eon would be 1.5x values given in the curves of figures 7 & 8. Turn-on
losses are measured over the integral period specified below:-
10 µs
Eon = iv.dt
0
The turn-on loss can be sub-divided into two component parts, firstly that associated with tgt and secondly
the contribution of the voltage tail. For this series of devices tgt contributes 50% and the voltage tail 50%
(These figures are approximate and are influenced by several second order effects). The loss during tgt is
greatly affected by gate current and as with turn-on time (figure 9), it can be reduced by increasing IGM.
The turn-on loss associated with the voltage tail is not effected by the gate conditions and can only be
reduced by limiting di/dt, where appropriate a turn-on snubber should be used. In applications where the
snubber is discharged through the GTO thyristor at turn-on, selection of discharge resistor will effect Eon.
The curves of figure 8 are given for a snubber as shown in diagram 2, with R=5, this is the lowest
recommended value giving the highest Eon, higher values will reduce Eon.
2.7 Turn-off characteristics
The basic circuit used for the turn-off test is given in diagram 10. Prior to the negative gate pulse being
applied constant current, equivalent to ITGQ, is established in the DUT. The switch Sx is opened just before
DUT is gated off with a reverse gate pulse as specified in the characteristic/data curves. After the period
tgt voltage rises across the DUT, dv/dt being limited by the snubber circuit. Voltage will continue to rise
across DUT until Dc turns-on at a voltage set by the active clamp Cc, the voltage will be held at this value
until energy stored in Lx is depleted, after which it will fall to VDC .The value of Lx is selected to give
required VD Over the full tail time period. The overshoot voltage VDM is derived from Lc and forward voltage
characteristic of DC, typically VDM=1.2VD to 1.5VD depending on test settings. The gate is held reverse
biased through a low impedance circuit until the tail current is fully extinguished.
Lc
Dc
Sx RL
Lx Rs
CT Ds
Vd
i DX
Cs Cd
Gate- DUT
drive
Cc
Vc
RCD snubber
Diagram 10, Turn-off test circuit.
The definitions of turn-off parameters used in the characteristic data are given in diagram 11.
Data Sheet. Type H0500KC25# Issue 2
Page 7 of 15
August, 2004

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