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부품번호 DT28F016SV
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DT28F016SV 데이터시트, 핀배열, 회로
16-MBIT (1 MBIT x 16, 2 MBIT x 8)
FlashFile™ MEMORY
Includes Commercial and Extended Temperature Specifications
n SmartVoltage Technology
User-Selectable 3.3V or 5V VCC
User-Selectable 5V or 12V VPP
n 65 ns Access Time
n 1 Million Erase Cycles per Block
n 30.8 MB/sec Burst Write Transfer Rate
n 0.48 MB/sec Sustainable Write Transfer
n Configurable x8 or x16 Operation
n 56-Lead TSOP and SSOP Type I
n Backwards-Compatible with 28F016SA,
28F008SA Command Set
n Revolutionary Architecture
Multiple Command Execution
Program during Erase
Command Super-Set of the Intel
Page Buffer Program
n 2 µA Typical Deep Power-Down
n 32 Independently Lockable Blocks
n State-of-the-Art 0.6 µm ETOX™ IV Flash
Intel’s 28F016SV 16-Mbit FlashFile™ memory is a revolutionary architecture which is the ideal choice for
designing embedded direct-execute code and mass storage data/file flash memory systems. With innovative
capabilities, low-power operation, user-selectable VPP voltage and high read/program performance, the
28F016SV enables the design of truly mobile, high-performance personal computing and communications
The 28F016SV is the highest density, highest performance nonvolatile read/program solution for solid-state
storage applications. Its symmetrically-blocked architecture (100% compatible with the 28F008SA 8-Mbit and
28F016SA 16-Mbit FlashFile memories), extended cycling, flexible VCC and VPP voltage (SmartVoltage
technology), fast program and read performance and selective block locking, provide a highly-flexible memory
component suitable for Resident Flash Arrays, high-density memory cards and PCMCIA-ATA flash drives.
The 28F016SV’s dual read voltage enables the design of memory cards which can be read/written in 3.3V
and 5V systems interchangeably. Its x8/x16 architecture allows optimization of the memory-to-processor
interface. The flexible block locking option enables bundling of executable application software in a Resident
Flash Array or memory card. The 28F016SV is manufactured on Intel’s 0.6 µm ETOX IV process technology.
July 1997
Order Number: 290528-007
7/11/97 11:03 AM 29052807.DOC

DT28F016SV pdf, 반도체, 판매, 대치품
28F016SV FlashFile™ MEMORY
Original Version
Added 28F016SV-065/-070 at 5V VCC and 28F016SV-075 at 3.3V VCC.
Improved burst write transfer rate to 30.8 MB/sec.
Added 56-lead SSOP Type I packaging information.
Changed VPPLK from 2V to 1.5V.
Increased ICCR at 5V VCC and 3.3V VCC:
ICCR1 from 30 mA (typ)/35 mA (max) to 40 mA (typ)/50 mA (max) @ VCC = 3.3V
ICCR2 from 15 mA (typ)/20 mA (max) to 20 mA (typ)/30 mA (max) @ VCC = 3.3V
ICCR1 from 50 mA (typ)/60 mA (max) to 75 mA (typ)/95 mA (max) @ VCC = 5V
ICCR2 from 30 mA (typ)/35 mA (max) to 45 mA (typ)/55 mA (max) @ VCC = 5V
Moved AC Characteristics for Extended Register Reads into separate table.
Increased VPP MAX from 13V to 14V.
Added Erase Suspend Command Latency times to Section 5.12
Modified Device Nomenclature Section to include SSOP package option and Ordering
Changed definition of “NC.” Removed “No internal connection to die” from description.
Added “xx” to Upper Byte of Command (Data) Definition in Sections 4.3 and 4.4.
Added Note to Sleep Command (Section 4.4) denoting that the chip must be de-selected
in order for the power consumption in sleep mode to reach deep power-down
Modified parameters “V” and “I” of Section 5.1 to apply to “NC” pins.
Increased IPPR (VPP Read Current) for VPP> VCC to 200 µA at VCC = 3.3V and VCC = 5V
Changed VCC = 5V DC Characteristics (Section 5.5) marked with Note 1 to indicate
that these currents are specified for a CMOS rise/fall time (10% to 90%) of <5 ns
and a TTL rise/fall time of <10 ns.
Corrected the graphical representation of tWHGL and tEHGL in Figures 15 and 16.
Increased Typical “Page Buffer Byte/Word Program Times” from 6.0 µs to 8.0 µs (Byte)
and 12.1 µs to 16.0 µs (Word) @ VCC = 3.3V/5V and VPP = 5V:
Increased Typ. “Byte/Word Program Times” (tWHRH1A/tWHRH1B) for VPP = 5V (Section
tWHRH1A from 16.5 µs to 29.0 µs and tWHRH1B from 24.0 µs to 35.0 µs at VCC =3.3V
tWHRH1A from 11.0 µs to 20.0 µs and tWHRH1B from 16.0 µs to 25.0 µs at VCC = 5V
Increased Typical “Block Program Times” (t WHRH2/tWHRH3)for VPP =5V (Section 5.12):
t WHRH2 from 1.1 sec to 1.9 sec and t WHRH3 from 0.8 sec to 1.2 sec at VCC = 3.3V
t WHRH2 from 0.8 sec to 1.4 sec and t WHRH3 from 0.6 sec to 0.85 sec at VCC = 5V
Changed “Time from Erase Suspend Command to WSM Ready” spec name to “Erase
Suspend Latency Time to Read;” modified typical values and added Min/Max
values at VCC =3.3/5V and VPP =5V/12V (Section 5.12)
Added “Erase Suspend Latency Time to Program” Specifications to Section 5.12
Minor cosmetic changes throughout document


DT28F016SV 전자부품, 판매, 대치품
The documentation of the Intel 28F016SV memory
device includes this datasheet, a detailed user’s
manual, and a number of application notes and
design tools, all of which are referenced in
Appendix B.
The datasheet is intended to give an overview of
the chip feature-set and of the operating AC/DC
specifications. The 16-Mbit Flash Product Family
User’s Manual provides complete descriptions of
the user modes, system interface examples and
detailed descriptions of all principles of operation.
It also contains the full list of software algorithm
flowcharts, and a brief section on compatibility
with the Intel 28F008SA.
A significant 28F016SV change occurred between
datasheet revisions 290528-003 and 290528-004.
This change centers around the addition of a 3/5#
pin to the device’s pinout configuration. Figures 2
and 3 show the 3/5# pin assignment for TSOP and
SSOP Type 1 packages. Intel recommends that all
customers obtain the latest revisions of 28F016SV
1.1 Enhanced Features
The 28F016SV is backwards compatible with the
28F016SA and offers the following enhancements:
SmartVoltage Technology
Selectable 5V or 12V VPP
VPP Level Bit in Block Status Register
Additional RY/BY# Configuration
Additional Upload Device Information
Command Feedback
Device Proliferation Code
Device Configuration Code
1.2 Product Overview
The 28F016SV is a high-performance, 16-Mbit
(16,777,216-bit) block erasable, nonvolatile
random access memory, organized as either
1 Mword x 16 or 2 Mbyte x 8. The 28F016SV
includes thirty-two 64-KB (65,536 byte) blocks or
thirty-two 32-KW (32,768 word) blocks. A chip
memory map is shown in Figure 4.
28F016SV FlashFile™ MEMORY
The implementation of a new architecture, with
many enhanced features, will improve the device
operating characteristics and result in greater
product reliability and ease-of-use.
The 28F016SV incorporates SmartVoltage
technology, providing VCC operation at both 3.3V
and 5V and program and erase capability at VPP =
12V or 5V. Operating at VCC = 3.3V, the
28F016SV consumes approximately one half the
power consumption at 5V VCC, while 5V VCC
provides the highest read performance capability.
VPP = 5V operation eliminates the need for a
separate 12V converter, while VPP = 12V
maximizes program/erase performance. In
addition to the flexible program and erase
voltages, the dedicated VPP gives complete code
protection with VPP VPPLK.
A 3/5# input pin configures the device’s internal
circuitry for optimal 3.3V or 5V read/program
A Command User Interface (CUI) serves as the
system interface between the microprocessor or
microcontroller and the internal memory operation.
Internal Algorithm Automation allows byte/word
programs and block erase operations to be
executed using a Two-Program command
sequence to the CUI in the same way as the
28F008SA 8-Mbit FlashFile™ memory.
A super-set of commands has been added to the
basic 28F008SA command-set to achieve higher
program performance and provide additional
capabilities. These new commands and features
Page Buffer Programs to Flash
Command Queuing Capability
Automatic Data Programs during Erase
Software Locking of Memory Blocks
Two-Byte Successive Programs in 8-bit
Erase All Unlocked Blocks
Writing of memory data is performed in either byte
or word increments typically within 6 µs
(12V VPP)—a 33% improvement over the
28F008SA. A block erase operation erases one of
the 32 blocks in typically 0.6 sec (12V VPP),
independent of the other blocks, which is about a
65% improvement over the 28F008SA.


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