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DT28F320S3 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 DT28F320S3
기능 WORD-WIDE FlashFile MEMORY
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DT28F320S3 데이터시트, 핀배열, 회로
E
ADVANCE INFORMATION
WORD-WIDE
FlashFile™ MEMORY FAMILY
28F160S3, 28F320S3
Includes Extended Temperature Specifications
n Two 32-Byte Write Buffers
2.7 µs per Byte Effective
Programming Time
n Low Voltage Operation
2.7V or 3.3V VCC
2.7V, 3.3V or 5V VPP
n 100 ns Read Access Time (16 Mbit)
110 ns Read Access Time (32 Mbit)
n High-Density Symmetrically-Blocked
Architecture
32 64-Kbyte Erase Blocks (16 Mbit)
64 64-Kbyte Erase Blocks (32 Mbit)
n System Performance Enhancements
STS Status Output
n Industry-Standard Packaging
µBGA* package, SSOP, and
TSOP (16 Mbit)
µBGA* package and SSOP (32 Mbit)
n Cross-Compatible Command Support
Intel Standard Command Set
Common Flash Interface (CFI)
Scaleable Command Set (SCS)
n 100,000 Block Erase Cycles
n Enhanced Data Protection Features
Absolute Protection with VPP = GND
Flexible Block Locking
Block Erase/Program Lockout
during Power Transitions
n Configurable x8 or x16 I/O
n Automation Suspend Options
Program Suspend to Read
Block Erase Suspend to Program
Block Erase Suspend to Read
n ETOX™ V Nonvolatile Flash
Technology
Intel’s Word-Wide FlashFile™ memory family provides high-density, low-cost, non-volatile, read/write storage
solutions for a wide range of applications. The Word-Wide FlashFile memories are available at various
densities in the same package type. Their symmetrically-blocked architecture, flexible voltage, and extended
cycling provide highly flexible components suitable for resident flash arrays, SIMMs, and memory cards.
Enhanced suspend capabilities provide an ideal solution for code or data storage applications. For secure
code storage applications, such as networking, where code is either directly executed out of flash or
downloaded to DRAM, the Word-Wide FlashFile memories offer three levels of protection: absolute protection
with VPP at GND, selective block locking, and program/erase lockout during power transitions. These
alternatives give designers ultimate control of their code security needs.
This family of products is manufactured on Intel’s 0.4 µm ETOX™ V process technology. It comes in the
industry-standard 56-lead SSOP and µBGA packages. In addition, the 16-Mb device is available in the
industry-standard 56-lead TSOP package.
June 1997
Order Number: 290608-001




DT28F320S3 pdf, 반도체, 판매, 대치품
28F160S3, 28F320S3
Number
-001
REVISION HISTORY
Description
Original version
E
4 ADVANCE INFORMATION

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DT28F320S3 전자부품, 판매, 대치품
E
28F160S3, 28F320S3
Sym
A0–A21
DQ0
DQ15
CE0#,
CE1#
RP#
OE#
WE#
STS
WP#
BYTE#
VPP
VCC
GND
NC
Table 1. Pin Descriptions
Type
Name and Function
INPUT ADDRESS INPUTS: Address inputs for read and write operations are internally
latched during a write cycle. A0 selects high or low byte when operating in x8 mode.
In x16 mode, A0 is not used; input buffer is off.
16-Mbit A0–A20 32-Mbit A0–A21
INPUT/ DATA INPUTS/OUTPUTS: Inputs data and commands during CUI write cycles;
OUTPUT outputs data during memory array, Status Register, query and identifier code read
cycles. Data pins float to high-impedance when the chip is deselected or outputs
are disabled. Data is internally latched during a write cycle.
INPUT
INPUT
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and
sense amplifiers. With CE0# or CE1# high, the device is deselected and power
consumption reduces to standby levels. Both CE0# and CE1# must be low to select
the device. Device selection occurs with the latter falling edge of CE0# or CE1#. The
first rising edge of CE0# or CE1# disables the device.
RESET/DEEP POWER-DOWN: When driven low, RP# inhibits write operations
which provides data protection during system power transitions, puts the device in
deep power-down mode, and resets internal automation. RP#-high enables normal
operation. Exit from deep power-down sets the device to read array mode.
INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
INPUT WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data
are latched on the rising edge of the WE# pulse.
OPEN
DRAIN
OUTPUT
STATUS: Indicates the status of the internal state machine. When configured in
level mode (default), it acts as a RY/BY# pin. For this and alternate configurations
of the STATUS pin, see the Configuration command. Tie STS to VCC with a pull-up
resistor.
INPUT WRITE PROTECT: Master control for block locking. When VIL, locked blocks
cannot be erased or programmed, and block lock-bits cannot be set or cleared.
INPUT BYTE ENABLE: Configures x8 mode (low) or x16 mode (high).
SUPPLY BLOCK ERASE, PROGRAM, LOCK-BIT CONFIGURATION POWER SUPPLY:
Necessary voltage to perform block erase, program, and lock-bit configuration
operations. Do not float any power pins.
SUPPLY DEVICE POWER SUPPLY: Do not float any power pins. Do not attempt block
erase, program, or block-lock configuration with invalid VCC values.
SUPPLY GROUND: Do not float any ground pins.
NO CONNECT: Lead is not internally connected; it may be driven or floated.
ADVANCE INFORMATION
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부품번호상세설명 및 기능제조사
DT28F320S3

WORD-WIDE FlashFile MEMORY

Intel
Intel

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