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PDF IXDD504 Data sheet ( Hoja de datos )
| Número de pieza | IXDD504 | |
| Descripción | 4 Ampere Dual Low-Side Ultrafast MOSFET Drivers | |
| Fabricantes | IXYS | |
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IXDD504/ IXDE504
4 Ampere Dual Low-Side Ultrafast MOSFET Drivers
with Enable for fast, controlled shutdown
Features
• Built using the advantages and compatibility
of CMOS and IXYS HDMOSTM processes
• Latch-Up Protected up to 4 Amps
• High 4A Peak Output Current
• Wide Operating Range: 4.5V to 30V
• -55°C to +125°C Extended Operating
Temperature
• Ability to Disable Output under Faults
• High Capacitive Load
Drive Capability: 1800pF in <15ns
• Matched Rise And Fall Times
• Low Propagation Delay Time
• Low Output Impedance
• Low Supply Current
• Two Drivers in a Single Package
Applications
• Limiting di/dt under Short Circuit
• Driving MOSFETs and IGBTs
• Motor Controls
• Line Drivers
• Pulse Generators
• Local Power ON/OFF Switch
• Switch Mode Power Supplies (SMPS)
• DC to DC Converters
• Pulse Transformer Driver
• Class D Switching Amplifiers
• Power Charge Pumps
General Description
The IXDD504 and IXDE504 each consist of two 4-Amp
CMOS high speed MOSFET gate drivers for driving the
latest IXYS MOSFETs & IGBTs. Each of the dual outputs
can source and sink 4 Amps of peak current while produc-
ing voltage rise and fall times of less than 15ns. The input
of each driver is TTL or CMOS compatible and is virtually
immune to latch up. Patented* design innovations eliminate
cross conduction and current "shoot-through". Improved
speed and drive capabilities are further enhanced by fast,
matched rise and fall times.
Additionally, each IXDD504 or IXDE504 driver incorporates a
unique ability to disable the output under fault conditions.
When a logical low is forced into the Enable input of a
driver, both of it's final output stage MOSFETs (NMOS and
PMOS) are turned off. As a result, the respective output of
the IXDD504 enters a tristate mode and, with additional
cicuitry, achieves a soft turn-off of the MOSFET/IGBT when
a short circuit is detected. This helps prevent damage that
could occur to the MOSFET/IGBT if it were to be switched
off abruptly due to a dv/dt over-voltage transient.
The IXDD504 and IXDE504 are each available in the 8-Pin
P-DIP (PI) package, the 8-Pin SOIC (SIA) package, and the
8-Lead DFN (D2) package, (which occupies less than 65%
of the board area of the 8-Pin SOIC).
*United States Patent 6,917,227
Ordering Information
Part Number
Description
IXDD504PI
IXDD504SIA
IXDD504SIAT/R
IXDD504D2
IXDD504D2T/R
IXDE504PI
IXDE504SIA
IXDE504SIAT/R
IXDE504D2
IXDE504D2T/R
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
4A Low Side Gate Driver I.C.
Package
Type
8-Pin PDIP
8-Pin SOIC
8-Pin SOIC
8-Lead DFN
8-Lead DFN
8-Pin PDIP
8-Pin SOIC
8-Pin SOIC
8-Lead DFN
8-Lead DFN
Packing Style
Tube
Tube
13” Tape and Reel
2” x 2” Waffle Pack
13” Tape and Reel
Tube
Tube
13” Tape and Reel
2” x 2” Waffle Pack
13” Tape and Reel
Pack
Qty
50
94
2500
56
2500
50
94
2500
56
2500
Configuration
Dual Non-
Inverting
Drivers with
Enable
Dual Inverting
Drivers
Inverting with
Enable
NOTE: All parts are lead-free and RoHS Compliant
Copyright © 2007 IXYS CORPORATION All rights reserved
First Release
DS99568A(10/07)
1 page  
IXDD504 / IXDE504
Pin Description
SYMBOL
EN A
IN A
GND
IN B
OUT B
VCC
OUT A
EN B
FUNCTION
A Channel Enable
A Channel Input
Ground
B Channel Input
B Channel Output
Supply Voltage
A Channel Output
B Channel Enable
DESCRIPTION
Channel A enable pin. When driven low, this pin disables the A channel and
forces a high impedance state to the A channel output.
A channel input signal-TTL or CMOS compatible.
The system ground pin. Internally connected to all circuitry, this pin provides
ground reference for the entire chip. This pin should be connected to a low
noise analog ground plane for optimum performance.
B channel input signal-TTL or CMOS compatible.
B channel driver output. For application purposes, this pin is connected via a
resistor to the gate of a MOSFET/IGBT.
Positive power-supply voltage input. This pin provides power to the entire
chip. The range for this voltage is from 4.5V to 30V.
A channel driver output. For application purposes, this pin is connected via a
resistor to the gate of a MOSFET/IGBT.
Channel B enable pin. When driven low, this pin disables the B channel and
forces a high impedance state to the B channel output.
CAUTION: Follow proper ESD procedures when handling and assembling this component.
Pin Configurations
8 PIN DIP (PI)
8 PIN SOIC (SIA)
8 PIN DIP (PI)
8 PIN SOIC (SIA)
1 EN A
2 IN A
3 GND
4 IN B
I EN B 8
X
D OUT A 7
D
5 VCC 6
0
4 OUT B 5
EN A 1
IN A 2
GND 3
IN B 4
I 8 EN B
X
D 7 OUT A
E
5 6 VCC
0
4 5 OUT B
8 LEAD DFN (D2)
(Bottom View)
OUT A 8 I 1 EN A
X
GND 7 D 2 IN A
D
V C C 6 5 3 IN B
0
OUT B 5 4 4 EN B
8 LEAD DFN (D2)
(Bottom View)
OUT A 8
I
1 EN A
X
GND 7 D 2 IN A
E
VCC 6
5
3 IN B
0
OUT B 5
4
4 EN B
NOTE: Solder tabs on bottoms of DFN packages are grounded
Figure 3 - Characteristics Test Diagram
VIN
IXYS reserves the right to change limits, test conditions, and dimensions.
5
5 Page 
IXDD504 / IXDE504
APPLICATIONS INFORMATION
Short Circuit di/dt Limit
A short circuit in a high-power MOSFET such as the IXFN100N20,
(20A, 1000V), as shown in Figure 32, can cause the current
through the module to flow in excess of 60A for 10µs or more
prior to self-destruction due to thermal runaway. For this
reason, some protection circuitry is needed to turn off the
MOSFET module. However, if the module is switched off too
fast, there is a danger of voltage transients occuring on the
drain due to Ldi/dt, (where L represents total inductance in
series with drain). If these voltage transients exceed the
MOSFET's voltage rating, this can cause an avalanche break-
down.
The IXDD504 and IXDE504 have the unique capability, with
additional circuitry, to softly switch off the high-power MOSFET
module, significantly reducing these Ldi/dt transients.
Thus, the IXDD504 & IXDE504 help to prevent device destruc-
tion from both dangers; over-current, and avalanche break-
down due to di/dt induced over-voltage transients.
The IXDD504 & IXDE504 are designed to not only provide ±4A
per output under normal conditions, but also to allow their
outputs to go into a high impedance state. This permits the
IXDD504 or IXDE504 outputs to control a separate weak pull-
down circuit during detected overcurrent shutdown conditions
to limit and separately control d /dt gate turnoff. This circuit
VGS
is shown in Figure 33.
Referring to Figure 33, the protection circuitry should include
a comparator, whose positive input is connected to the source
of the IXFN100N20. A low pass filter should be added to the
input of the comparator to eliminate any glitches in voltage
caused by the inductance of the wire connecting the source
resistor to ground. (Those glitches might cause false triggering
of the comparator).
The comparator's output should be connected to a SRFF(Set
Reset Flip Flop). The flip-flop controls both the Enable signal,
and the low power MOSFET gate. Please note that CMOS 4000-
series devices operate with a VCC range from 3 to 15 VDC, (with
18 VDC being the maximum allowable limit).
A low power MOSFET, such as the 2N7002, in series with a
resistor, will enable the IXFN100N20 gate voltage to drop
gradually. The resistor should be chosen so that the RC time
constant will be 100us, where "C" is the Miller capacitance of
the IXFN100N20.
For resuming normal operation, a Reset signal is needed at
the SRFF's input to enable the IXDD504 again. This Reset can
be generated by connecting a One Shot circuit between the
IXDD504 Input signal and the SRFF restart input. The One Shot
will create a pulse on the rise of the IXDD504 input, and this
pulse will reset the SRFF outputs to normal operation.
When a short circuit occurs, the voltage drop across the low-
value, current-sensing resistor, (Rs=0.005 Ohm), connected
between the MOSFET Source and ground, increases. This
triggers the comparator at a preset level. The SRFF drives a low
input into the Enable pin disabling the IXDD504 output. The
SRFF also turns on the low power MOSFET, (2N7000).
In this way, the high-power MOSFET module is softly turned off
by the IXDD504, preventing its destruction.
Figure 33 - Application Test Diagram
+ VCC + VIN
--
IXDD504
VCC
IN
EN
DGND
OUT
One Shot Circuit
NOT1
CD4049A
Ros
1M
NAND
NOT2
CD4011A CD4049A
Cos
1pF
Q
Rcomp
5k
Ccomp
1pF
R
NOT3
CD4049A
NOR1
CD4001A
S
EN
Rsh
1600
Ld
10uH
+ VB
-
Rd
0.1
Rg
IXFN100N20
1
Low_Power
2N7000
R+
10k
Rs
Ls
20nH
Comp
LM339 +
V+
V-
-
+
-
REF
C+
100pF
NOR2
CD4001A
SR Flip-Flop
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet IXDD504.PDF ] | |
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