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BZA109 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 BZA109
기능 9-fold ESD transient voltage suppressor
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BZA109 데이터시트, 핀배열, 회로
DISCRETE SEMICONDUCTORS
DATA SHEET
ndbook, halfpage
M3D184
BZA109
9-fold ESD transient voltage
suppressor
Product specification
Supersedes data of 1997 Oct 27
File under Discrete Semiconductors, SC01
1997 Dec 01




BZA109 pdf, 반도체, 판매, 대치품
Philips Semiconductors
9-fold ESD transient voltage suppressor
Product specification
BZA109
GRAPHICAL DATA
10
handbook, halfpage
IZSM
(A)
MBK269
handbook2, .h0alfpage
Ptot
(W)
1.5
MBK393
1.0
0.5
1101
1
tp (ms)
10
0
0 50 100 150 200
Tamb (°C)
Fig.2 Maximum non-repetitive peak reverse
current as a function of pulse time.
One or more diodes loaded.
Fig.3 Power derating curve.
102
handbook, halfpage
PZSM
(W)
MBK270
handboo1k,5h0alfpage
Cd
(pF)
100
MBK272
50
10
101
1
tp (ms)
10
PZSM = VZSM × IZSM.
VZSM is the non-repetitive peak reverse voltage at IZSM.
Fig.4 Maximum non-repetitive peak reverse power
dissipation as a function of pulse duration
(square pulse).
0
0 2 4 VR (V) 6
Tj = 25 °C; f = 1 MHz.
Fig.5 Diode capacitance as a function of reverse
voltage; typical values.
1997 Dec 01
4

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BZA109 전자부품, 판매, 대치품
Philips Semiconductors
9-fold ESD transient voltage suppressor
Product specification
BZA109
Device placement and printed-circuit board layout
Circuit board layout is of extreme importance in the suppression of transients. The clamping voltage of the BZA109 is
determined by the peak transient current and the rate of rise of that current (di/dt). Since parasitic inductances can further
add to the clamping voltage (V = L di/dt) the series conductor lengths on the printed-circuit board should be kept to a
minimum. This includes the lead length of the suppression element.
In addition to minimizing conductor length the following printed-circuit board layout guidelines are recommended:
1. Place the suppression element close to the input terminals or connectors.
2. Keep parallel signal paths to a minimum.
3. Avoid running protection conductors in parallel with unprotected conductors.
4. Minimize all printed-circuit board loop areas including power and ground loops.
5. Minimize the length of the transient return path to ground.
6. Avoid using shared transient return paths to a common ground point.
1997 Dec 01
7

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