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부품번호 | BUK108-50GL 기능 |
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기능 | PowerMOS transistor Logic level TOPFET | ||
제조업체 | NXP Semiconductors | ||
로고 | |||
Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK108-50GL
DESCRIPTION
Monolithic temperature and
overload protected logic level power
MOSFET in a 3 pin plastic surface
mount envelope, intended as a
general purpose switch for
automotive systems and other
applications.
APPLICATIONS
General controller for driving
lamps
motors
solenoids
heaters
QUICK REFERENCE DATA
SYMBOL PARAMETER
VDS
ID
PD
Tj
RDS(ON)
Continuous drain source voltage
Continuous drain current
Total power dissipation
Continuous junction temperature
Drain-source on-state resistance
VIS = 5 V
FEATURES
Vertical power DMOS output
stage
Low on-state resistance
Overload protection against
over temperature
Overload protection against
short circuit load
Latched overload protection
reset by input
5 V logic compatible input level
Control of power MOSFET
and supply of overload
protection circuits
derived from input
Low operating input current
ESD protection on input pin
Overvoltage clamping for turn
off of inductive loads
FUNCTIONAL BLOCK DIAGRAM
INPUT
O/V
CLAMP
RIG
LOGIC AND
PROTECTION
MAX.
50
13.5
40
150
125
UNIT
V
A
W
˚C
mΩ
DRAIN
POWER
MOSFET
SOURCE
PINNING - SOT404
PIN DESCRIPTION
1 input
2 drain
3 source
mb drain
Fig.1. Elements of the TOPFET.
PIN CONFIGURATION
SYMBOL
mb D
TOPFET
2
13
I
P
S
June 1996
1
Rev 1.000
Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK108-50GL
TRANSFER CHARACTERISTICS
Tmb = 25 ˚C
SYMBOL PARAMETER
gfs Forward transconductance
ID(SC)
Drain current1
CONDITIONS
VDS = 10 V; IDM = 7.5 A tp ≤ 300 µs;
δ ≤ 0.01
VDS = 13 V; VIS = 5 V
MIN. TYP. MAX. UNIT
59 -S
- 25 -
A
SWITCHING CHARACTERISTICS
Tmb = 25 ˚C. RI = 50 Ω . Refer to waveform figures and test circuits.
SYMBOL PARAMETER
CONDITIONS
td on Turn-on delay time
tr Rise time
td off Turn-off delay time
tf Fall time
td on Turn-on delay time
tr Rise time
td off Turn-off delay time
tf Fall time
VDD = 13 V; VIS = 5 V
resistive load RL = 4 Ω
VDD = 13 V; VIS = 0 V
resistive load RL = 4 Ω
VDD = 13 V; VIS = 5 V
inductive load IDM = 3 A
VDD = 13 V; VIS = 0 V
inductive load IDM = 3 A
MIN.
-
-
-
-
-
-
-
-
TYP.
1.5
8
6
4.5
1.5
1
10
0.5
MAX.
-
-
-
-
-
-
-
-
UNIT
µs
µs
µs
µs
µs
µs
µs
µs
REVERSE DIODE LIMITING VALUE
SYMBOL PARAMETER
IS Continuous forward current
CONDITIONS
Tmb ≤ 25 ˚C; VIS = 0 V
MIN.
-
MAX.
13.5
UNIT
A
REVERSE DIODE CHARACTERISTICS
Tmb = 25 ˚C
SYMBOL PARAMETER
CONDITIONS
VSDS
trr
Forward voltage
Reverse recovery time
IS = 15 A; VIS = 0 V; tp = 300 µs
not applicable2
MIN.
-
-
TYP. MAX. UNIT
1.0 1.5 V
---
ENVELOPE CHARACTERISTICS
SYMBOL PARAMETER
Ld Internal drain inductance
Ls Internal source inductance
CONDITIONS
Measured from upper edge of tab
to centre of die
Measured from source lead
soldering point to source bond pad
MIN. TYP. MAX. UNIT
- 2.5 - nH
- 7.5 - nH
1 During overload before short circuit load protection operates.
2 The reverse diode of this type is not intended for applications requiring fast reverse recovery.
June 1996
4
Rev 1.000
4페이지 Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK108-50GL
Energy & Time
1
0.5
Time / ms
BUK108-50GL
Energy / J
Tj(TO)
0
-60 -20 20
60 100 140 180 220
Tmb / C
Fig.14. Typical overload protection characteristics.
Conditions: VDD = 13 V; VIS = 5 V; SC load = 30 mΩ
ID / A
20
BUK108-50GL
15
typ.
10
5
0
50
60
VDS / V
70
Fig.15. Typical clamping characteristics, 25 ˚C.
ID = f(VDS); conditions: VIS = 0 V; tp ≤ 50 µs
VIS(TO) / V
2
1
max.
typ.
min.
0
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
Fig.16. Input threshold voltage.
VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V
IIS / uA
500
BUK108-50GL
400
300
25 C
200
100
150 C
0
02468
VIS / V
Fig.17. Typical DC input characteristics.
IIS = f(VIS); normal operation, parameter: Tj
10
IISL / mA
3
2
PROTECTION LATCHED
BUK108-50GL
RESET
1
NORMAL
0
0
246
VIS / V
8
Fig.18. Typical DC input characteristics, Tj = 25 ˚C.
IISL = f(VIS); overload protection operated ⇒ ID = 0 A
IS / A
60
BUK108-50GL
50
40
30
20
10
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4
VSD / V
Fig.19. Typical reverse diode current, Tj = 25 ˚C.
IS = f(VSDS); conditions: VIS = 0 V; tp = 250 µs
June 1996
7
Rev 1.000
7페이지 | |||
구 성 | 총 11 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
BUK108-50GL | PowerMOS transistor Logic level TOPFET | NXP Semiconductors |
BUK108-50GL | PowerMOS transistor Logic level TOPFET | NXP Semiconductors |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |