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부품번호 | BUK109-50DL 기능 |
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기능 | PowerMOS transistor Logic level TOPFET | ||
제조업체 | NXP Semiconductors | ||
로고 | |||
전체 10 페이지수
Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK109-50DL
DESCRIPTION
Monolithic temperature and
overload protected logic level power
MOSFET in a 3 pin plastic surface
mount envelope, intended as a
general purpose switch for
automotive systems and other
applications.
APPLICATIONS
General controller for driving
lamps
motors
solenoids
heaters
QUICK REFERENCE DATA
SYMBOL PARAMETER
VDS
ID
PD
Tj
RDS(ON)
Continuous drain source voltage
Continuous drain current
Total power dissipation
Continuous junction temperature
Drain-source on-state resistance
IISL
Input supply current
VIS = 5 V
FEATURES
Vertical power DMOS output
stage
Low on-state resistance
Overload protection against
over temperature
Overload protection against
short circuit load
Latched overload protection
reset by input
5 V logic compatible input level
Control of power MOSFET
and supply of overload
protection circuits
derived from input
Lower operating input current
permits direct drive by
micro-controller
ESD protection on input pin
Overvoltage clamping for turn
off of inductive loads
FUNCTIONAL BLOCK DIAGRAM
INPUT
O/V
CLAMP
RIG
LOGIC AND
PROTECTION
MAX.
50
26
75
150
60
650
UNIT
V
A
W
˚C
mΩ
µA
DRAIN
POWER
MOSFET
SOURCE
PINNING - SOT404
PIN DESCRIPTION
1 input
2 drain
3 source
mb drain
Fig.1. Elements of the TOPFET.
PIN CONFIGURATION
SYMBOL
mb D
TOPFET
2
13
I
P
S
June 1996
1
Rev 1.000
Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK109-50DL
INPUT CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified. The supply for the logic and overload protection is taken from the input.
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
VIS(TO)
IIS
VISR
IISL
V(BR)IS
RIG
Input threshold voltage
Input supply current
Protection reset voltage1
Input supply current
Input breakdown voltage
Input series resistance
to gate of power MOSFET
VDS = 5 V; ID = 1 mA
1.0 1.5 2.0
normal operation;
VIS = 5 V
100 200 350
VIS = 4 V
- 160 270
Tj = 25 ˚C 2.0 2.6 3.5
Tj = 150 ˚C 1.0
-
-
protection latched;
II = 10 mA
VIS = 5 V
VIS = 3.5 V
Tj = 25 ˚C
Tj = 150 ˚C
-
-
6
-
-
330 650
240 430
--
33 -
50 -
V
µA
µA
V
µA
µA
V
kΩ
kΩ
SWITCHING CHARACTERISTICS
Tmb = 25 ˚C. RI = 50 Ω . Refer to waveform figure and test circuit.
SYMBOL PARAMETER
CONDITIONS
td on Turn-on delay time
tr Rise time
td off Turn-off delay time
tf Fall time
VDD = 13 V; VIS = 5 V
resistive load RL = 2.1 Ω
VDD = 13 V; VIS = 0 V
resistive load RL = 2.1 Ω
MIN.
-
-
-
-
TYP.
17
75
60
70
MAX.
-
-
-
-
UNIT
µs
µs
µs
µs
REVERSE DIODE LIMITING VALUE
SYMBOL PARAMETER
IS Continuous forward current
CONDITIONS
Tmb ≤ 25 ˚C; VIS = 0 V
MIN.
-
MAX.
26
UNIT
A
REVERSE DIODE CHARACTERISTICS
Tmb = 25 ˚C
SYMBOL PARAMETER
CONDITIONS
VSDO
trr
Forward voltage
Reverse recovery time
IS = 26 A; VIS = 0 V; tp = 300 µs
not applicable2
MIN.
-
-
TYP. MAX. UNIT
1.0 1.5 V
---
ENVELOPE CHARACTERISTICS
SYMBOL PARAMETER
Ld Internal drain inductance
Ls Internal source inductance
CONDITIONS
Measured from upper edge of tab
to centre of die
Measured from source lead
soldering point to source bond pad
MIN. TYP. MAX. UNIT
- 2.5 - nH
- 7.5 - nH
1 The input voltage below which the overload protection circuits will be reset.
2 The reverse diode of this type is not intended for applications requiring fast reverse recovery.
June 1996
4
Rev 1.000
4페이지 Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK109-50DL
IISL & IIS / uA
600
BUK109-50DL
500 PROTECTION LATCHED
400
IISL
300 RESET
IIS
200
100 NORMAL
0
0246
VIS / V
Fig.14. Typical DC input characteristics, Tj = 25 ˚C.
IISL & IIS = f(VIS); protection latched & normal operation
IS / A
100
BUK109-50DL
50
0
0
Fig.15.
1
VSD / V
2
Typical reverse diode current, Tj = 25 ˚C.
IS = f(VSDS); conditions: VIS = 0 V
VDD
RL
D
TOPFET
I
P
D.U.T.
RI
VIS S
ID measure
0R1
0V
Fig.16. Test circuit for resistive load switching times.
VIS / V & VDS / V
15
VDS
10
5
VIS
BUK109-50DL
0
0 200 400 600
time / us
Fig.17. Typical switching waveforms, resistive load.
VDD = 13 V; RL = 2.1 Ω; RI = 50 Ω, Tj = 25 ˚C.
EDSM%
120
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Tmb / C
Fig.18. Normalised clamping energy rating.
EDSM% = f(Tmb); conditions: ID = 26 A; VIS = 5 V
VDS
0
ID
0
VIS
0
V(CL)DSS
VDD
L
+ VDD
VDS
D
TOPFET
I
P
D.U.T.
-
-ID/100
RIS
Schottky
S
R 01
shunt
Fig.19. Clamping energy test circuit, RIS = 50 Ω.
EDSM = 0.5 ⋅ L ID2 ⋅ V(CL)DSS/(V(CL)DSS − VDD)
June 1996
7
Rev 1.000
7페이지 | |||
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부품번호 | 상세설명 및 기능 | 제조사 |
BUK109-50DL | PowerMOS transistor Logic level TOPFET | NXP Semiconductors |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |