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Número de pieza BUK112-50GL
Descripción PowerMOS transistor Logic level TOPFET
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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No Preview Available ! BUK112-50GL Hoja de datos, Descripción, Manual

Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK112-50GL
DESCRIPTION
Monolithic temperature and
overload protected logic level power
MOSFET in a 5 pin plastic
envelope, intended as a low side
switch for automotive applications.
FEATURES
Vertical power DMOS output
stage
Low on-state resistance
Low operating supply current
Overtemperature protection
Overload protection against
short circuit load with
drain current limiting
Latched overload protection
reset by protection supply
Protection circuit condition
indicated by flag pin
Off-state detection
of open circuit load
indicated by flag pin
5 V logic compatible input level
Integral input resistors.
ESD protection on all pins
Over voltage clamping
QUICK REFERENCE DATA
SYMBOL PARAMETER
VDS
ID
Tj
RDS(ON)
SYMBOL
Continuous drain source voltage
Continuous drain current
Continuous junction temperature
Drain-source on-state resistance
PARAMETER
VPS Protection supply voltage
FUNCTIONAL BLOCK DIAGRAM
PROTECTION SUPPLY
FLAG
INPUT
OC LOAD
DETECT
RIG
O/V
CLAMP
LOGIC AND
PROTECTION
RIS
MAX.
50
12
150
93
NOM.
5
UNIT
V
A
˚C
m
UNIT
V
DRAIN
POWER
MOSFET
SOURCE
PINNING - SOT263
PIN DESCRIPTION
1 input
2 flag
3 drain
4 protection supply
5 source
tab drain
Fig.1. Elements of the TOPFET.
PIN CONFIGURATION
SYMBOL
tab
1 2345
leadform
263-01
Fig. 2.
TOPFET
P
FP
I
D
S
Fig. 3.
September 1996
1
Rev 1.000

1 page




BUK112-50GL pdf
Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK112-50GL
OVERLOAD CHARACTERISTICS
Tmb = 25 ˚C; VPS = 5 V unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
ID
PD(TO)
EDSC
IDM
Tj(TO)
Short circuit load protection
Drain current limiting
Overload power threshold1
Characteristic energy
Peak drain current3
Overtemperature protection
Threshold temperature
VIS = 5 V
VDS = 13 V -40˚C Tmb 150˚C
for protection to operate
which determines trip time2
VDD = 13 V; RL 10 m
ID 1 A
FLAG CHARACTERISTICS
The flag is an open drain transistor which requires an external pull-up circuit.
Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
Flag ‘low’
VFSF Flag voltage
IFSF Flag saturation current
Flag ‘high’
normal operation; VPS = 5 V
IF = 100 µA
-40˚C Tmb 150˚C
VFS = 5 V
overload or fault
IFSO
V(CL)FS
Flag leakage current
Flag clamping voltage
VFS = 5 V
IF = 100 µA
Tmb = 150˚C
VPSF
Protection supply threshold
IF = 100 µA; VDS = 5 V
voltage4
-40˚C Tmb 150˚C
Application information
RF
Suitable external pull-up
VFF = 5 V
resistance
MIN. TYP. MAX. UNIT
12 24 36
A
- 100 -
W
- 200 - mJ
- 45 -
A
150 185 215 ˚C
MIN. TYP. MAX. UNIT
- 0.7 -
V
- - 0.9 V
- 10 - mA
- 0.1 1 µA
- 1 10 µA
6 6.9 -
V
2.5 3 4 V
2 - 4V
- 50 - k
1 Refer to figure 15.
2 Trip time td sc EDSC / [ PD - PD(TO) ]. Refer also to figure 15.
3 For short circuit load connected after turn-on.
4 When VPS is less than VPSF the flag pin indicates low protection supply voltage. Refer to TRUTH TABLE.
September 1996
5
Rev 1.000

5 Page





BUK112-50GL arduino
Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
IF / mA
20
BUK112-50GL
15
10
5
0
0123456789
VFS / V
Fig.24. Typical flag saturation current, Tj = 25˚C.
IF = f(VFS); flag ’low’; external RF = 0 k; VPS = 5 V
VFSF / V
1
BUK112-50GL
0.8
0.6
0.4
0.2
0
-50 0 50 100 150 200
Tj / C
Fig.25. Typical flag low voltage.
VFSF = f(Tj); VPS = 5 V; VIS = 5 V; VDS = 0 V
VPSF / V
4
BUK112-50GL
3.5
typ.
3
2.5
2
-50 0 50 100 150 200
Tj / C
Fig.26. Protection supply threshold voltage.
VPSF = f(Tj); condition: VDS = 5 V
Product specification
BUK112-50GL
VPSR / V
3
BUK112-50GL
2.5
typ.
2
1.5
1
-50 0
50 100 150
Tj / C
Fig.27. Protection supply reset voltage.
VPSR = f(Tj)
200
IP / uA
600
BUK112-50GL
500
400
300
200
100
0
-50 0 50 100 150 200
Tmb / C
Fig.28. Typical protection supply current.
IP = f(Tj); VPS = 4.5 V
IS / A
40
BUK112-50GL
30
20
10
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4
VSD / V
Fig.29. Typical reverse diode current, Tj = 25˚C.
IS = f(VSD); conditions: VIS = 0 V; tp = 250 µs
September 1996
11
Rev 1.000

11 Page







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