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Número de pieza | BUK554-200A | |
Descripción | PowerMOS transistor Logic level FET | |
Fabricantes | NXP Semiconductors | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de BUK554-200A (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
No Preview Available ! Philips Semiconductors
PowerMOS transistor
Logic level FET
Product Specification
BUK554-200A/B
GENERAL DESCRIPTION
N-channel enhancement mode
logic level field-effect power
transistor in a plastic envelope.
The device is intended for use in
Switched Mode Power Supplies
(SMPS), motor control, welding,
DC/DC and AC/DC converters, and
in automotive and general purpose
switching applications.
PINNING - TO220AB
PIN DESCRIPTION
1 gate
2 drain
3 source
tab drain
QUICK REFERENCE DATA
SYMBOL PARAMETER
VDS
ID
Ptot
Tj
RDS(ON)
BUK554
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance;
VGS = 5 V
MAX.
-200A
200
9.2
90
175
0.4
PIN CONFIGURATION
SYMBOL
tab
MAX.
-200B
200
8.2
90
175
0.5
d
UNIT
V
A
W
˚C
Ω
1 23
g
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
VDS
VDGR
±VGS
±VGSM
Drain-source voltage
-
Drain-gate voltage
Gate-source voltage
RGS = 20 kΩ
-
Non-repetitive gate-source voltage tp ≤ 50 µs
-
-
-
-
ID Drain current (DC)
Tmb = 25 ˚C
ID Drain current (DC)
Tmb = 100 ˚C
IDM Drain current (pulse peak value) Tmb = 25 ˚C
Ptot Total power dissipation
Tstg Storage temperature
Tj Junction Temperature
Tmb = 25 ˚C
-
-
-
-
-
-
- 55
-
THERMAL RESISTANCES
SYMBOL
Rth j-mb
Rth j-a
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
MAX.
200
200
15
20
-200A
9.2
6.5
36
-200B
8.2
5.8
33
90
175
175
UNIT
V
V
V
V
A
A
A
W
˚C
˚C
MIN. TYP. MAX. UNIT
- - 1.67 K/W
- 60 - K/W
April 1993 1 Rev 1.100
1 page Philips Semiconductors
PowerMOS transistor
Logic level FET
VGS / V
12
10
BUK554-200
VDS / V =40
8
160
6
4
2
0
0 10 20 30 40
QG / nC
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 9.2 A; parameter VDS
IF / A
20
BUK554-200A
15
Tj / C = 150
25
10
5
0
012
VSDS / V
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Product Specification
BUK554-200A/B
WDSS%
120
110
100
90
80
70
60
50
40
30
20
10
0
20 40 60 80 100 120 140 160 180
Tmb / C
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 9 A
VGS
0
RGS
L
VDS
T.U.T.
+ VDD
-
-ID/100
R 01
shunt
Fig.16. Avalanche energy test circuit.
WDSS = 0.5 ⋅ LID2 ⋅ BVDSS/(BVDSS − VDD)
April 1993 5 Rev 1.100
5 Page |
Páginas | Total 7 Páginas | |
PDF Descargar | [ Datasheet BUK554-200A.PDF ] |
Número de pieza | Descripción | Fabricantes |
BUK554-200A | PowerMOS transistor Logic level FET | NXP Semiconductors |
BUK554-200A | PowerMOS transistor Logic level FET | NXP Semiconductors |
BUK554-200B | PowerMOS transistor Logic level FET | NXP Semiconductors |
BUK554-200B | PowerMOS transistor Logic level FET | NXP Semiconductors |
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