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PDF BUK7621-30 Data sheet ( Hoja de datos )

Número de pieza BUK7621-30
Descripción TrenchMOS transistor Standard level FET
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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Philips Semiconductors
TrenchMOStransistor
Standard level FET
Product specification
BUK7621-30
GENERAL DESCRIPTION
N-channel enhancement mode
standard level field-effect power
transistor in a plastic envelope
suitable for surface mounting using
trench’ technology. The device
features very low on-state resistance
and has integral zener diodes giving
ESD protection up to 2kV. It is
intended for use in automotive and
general purpose switching
applications.
PINNING - SOT404 (D2PAK)
PIN DESCRIPTION
1 gate
2 drain
3 source
mb drain
QUICK REFERENCE DATA
SYMBOL PARAMETER
VDS
ID
Ptot
Tj
RDS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
VGS = 10 V
MAX.
30
50
94
175
21
PIN CONFIGURATION
mb
2
13
SYMBOL
d
g
s
UNIT
V
A
W
˚C
m
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDS
VDGR
±VGS
ID
ID
IDM
Ptot
Tstg, Tj
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
-
RGS = 20 k
-
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
-
THERMAL RESISTANCES
SYMBOL
Rth j-mb
Rth j-a
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
-
pcb mounted, minimum
footprint
ESD LIMITING VALUE
SYMBOL
VC
PARAMETER
Electrostatic discharge capacitor
voltage, all pins
CONDITIONS
Human body model
(100 pF, 1.5 k)
MIN.
-
-
-
-
-
-
-
- 55
MAX.
30
30
20
50
29
200
94
175
UNIT
V
V
V
A
A
A
W
˚C
TYP.
-
50
MAX.
1.6
-
UNIT
K/W
K/W
MIN.
-
MAX.
2
UNIT
kV
July 1997
1 Rev 1.000

1 page




BUK7621-30 pdf
Philips Semiconductors
TrenchMOStransistor
Standard level FET
Product specification
BUK7621-30
1E-01
Sub-Threshold Conduction
1E-02
1E-03
2% typ
98%
1E-04
1E-05
1E-06
01234
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
5
Capacitances, Ciss, Coss, Crss (pF)
10000
PHP50N03T
1000
Ciss
Coss
100
1
Crss
10
Drain-source voltage, VDS (V)
100
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
VGS, Gate-Source voltage (Volts)
20
VDD = 30 V
ID = 25 A
Tj = 25 C
15
PHP50N03T
10
5
0
0 10 20 30 40 50 60
Qg, Gate charge (nC)
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); parameter VDS
Source-Drain diode current, IF(A)
50
VGS = 0 V
40
PHP50N03T
30
20
175 C
Tj = 25 C
10
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Source-Drain voltage, VSDS (V)
Fig.14. Typical reverse diode current.
IF = f(VSDS); parameter Tj
WDSS%
120
110
100
90
80
70
60
50
40
30
20
10
0
20 40 60 80 100 120 140 160 180
Tmb / C
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tmb)
VGS
0
RGS
L
VDS
T.U.T.
+ VDD
-
-ID/100
R 01
shunt
Fig.16. Avalanche energy test circuit.
WDSS = 0.5 LID2 BVDSS/(BVDSS VDD)
July 1997
5 Rev 1.000

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