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PDF BUK7880-55 Data sheet ( Hoja de datos )
| Número de pieza | BUK7880-55 | |
| Descripción | TrenchMOS transistor Standard level FET | |
| Fabricantes | NXP Semiconductors | |
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Philips Semiconductors
TrenchMOS™ transistor
Standard level FET
Product specification
BUK7880-55
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope suitable for surface
mounting. Using ’trench’ technolgy
the device features very low on-state
resistance and has integral zener
diodes giving ESD protection. It is
intended for use in automotive and
general purpose switching
applications.
QUICK REFERENCE DATA
SYMBOL PARAMETER
VDS
ID
Ptot
Tj
RDS(ON)
Drain-source voltage
Drain current
Total power dissipation
Junction temperature
Drain-source on-state
resistance
VGS = 10 V
MAX.
55
7.5
1.8
150
80
PINNING - SOT223
PIN DESCRIPTION
1 gate
2 drain
3 source
4 drain (tab)
PIN CONFIGURATION
4
123
SYMBOL
d
g
s
UNIT
V
A
W
˚C
mΩ
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDS
VDGR
±VGS
ID
ID
ID
IDM
Ptot
Ptot
Tstg, Tj
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Total power dissipation
Storage & operating temperature
-
RGS = 20 kΩ
-
Tsp = 25 ˚C
On PCB in Fig.2
Tamb = 25 ˚C
On PCB in Fig.2
Tamb = 100 ˚C
Tsp = 25 ˚C
Tsp = 25 ˚C
On PCB in Fig.2
Tamb = 25 ˚C
-
ESD LIMITING VALUE
SYMBOL
VC
PARAMETER
Electrostatic discharge capacitor
voltage
CONDITIONS
Human body model
(100 pF, 1.5 kΩ)
MIN.
-
-
-
-
-
-
-
-
-
- 55
MAX.
55
55
16
7.5
3.5
2.2
40
8.3
1.8
150
UNIT
V
V
V
A
A
A
A
W
W
˚C
MIN.
-
MAX.
2
UNIT
kV
April 1998 1 Rev 1.100
1 page  
Philips Semiconductors
TrenchMOS™ transistor
Standard level FET
Product specification
BUK7880-55
1E-01
Sub-Threshold Conduction
1E-02
1E-03
2% typ
98%
1E-04
1E-05
1E-06
01234
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
5
1
.9
.8
.7
.6
.5
.4 Ciss
.3
.2
.1
0
0.01
0.1
1 VDS/V 10
Coss
Crss
100
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
12
VDS/V
10
8
6
VDS = 14V
VDS = 44V
4
2
0
0
5 QG/nC
10
15
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 7 A; parameter VDS
40
IF/A
30
20
Tj/V =
150
25
10
0
0 0.5 1 VSDS/V 1.5 2
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
WDSS%
120
110
100
90
80
70
60
50
40
30
20
10
0
20 40 60 80 100 120 140
Tmb / C
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tsp); conditions: ID = 2.5 A
VGS
0
RGS
L
VDS
T.U.T.
+ VDD
-
-ID/100
R 01
shunt
Fig.16. Avalanche energy test circuit.
WDSS = 0.5 ⋅ LID2 ⋅ BVDSS/(BVDSS − VDD)
April 1998 5 Rev 1.100
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet BUK7880-55.PDF ] | |
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