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PDF BUK9575-100A Data sheet ( Hoja de datos )
| Número de pieza | BUK9575-100A | |
| Descripción | TrenchMOS transistor Logic level FET | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
BUK9575-55
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope using ’trench’
technology. The device features very
low on-state resistance and has
integral zener diodes giving ESD
protection up to 2kV. It is intended for
use in automotive and general
purpose switching applications.
QUICK REFERENCE DATA
SYMBOL PARAMETER
VDS
ID
Ptot
Tj
RDS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
VGS = 5 V
MAX.
55
19.7
61
175
75
PINNING - TO220AB
PIN DESCRIPTION
1 gate
2 drain
3 source
tab drain
PIN CONFIGURATION
tab
1 23
SYMBOL
d
g
s
UNIT
V
A
W
˚C
mΩ
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDS
VDGR
±VGS
ID
ID
IDM
Ptot
Tstg, Tj
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
-
RGS = 20 kΩ
-
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
-
ESD LIMITING VALUE
SYMBOL
VC
PARAMETER
Electrostatic discharge capacitor
voltage, all pins
CONDITIONS
Human body model
(100 pF, 1.5 kΩ)
THERMAL RESISTANCES
SYMBOL
Rth j-mb
Rth j-a
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
-
in free air
MIN.
-
-
-
-
-
-
-
- 55
MAX.
55
55
10
19.7
13.9
79
61
175
UNIT
V
V
V
A
A
A
W
˚C
MIN.
-
MAX.
2
UNIT
kV
TYP.
-
60
MAX.
2.46
-
UNIT
K/W
K/W
April 1998 1 Rev 1.100
1 page  
Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
BUK9575-55
1E-01
Sub-Threshold Conduction
1E-02
1E-03
2% typ 98%
1E-04
1E-05
1E-05
0 0.5 1 1.5 2 2.5
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
3
1
.9
.8
.7
.6
.5 Ciss
.4
.3
.2
.1
0
0.01
0.1
1 VDS/V 10
Coss
Crss
100
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
6
VGS/V
5
4
3
VDS = 14V
VDS = 44V
2
1
0
0
2
4
6 QG/nC 8
10 12
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 20 A; parameter VDS
100
IF/A
80
60
Tj/C = 175
25
40
20
0
0 0.5 1 1.5
VSDS/V
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
WDSS%
120
110
100
90
80
70
60
50
40
30
20
10
0
20 40 60 80 100 120 140 160 180
Tmb / C
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 17 A
VGS
0
RGS
L
VDS
T.U.T.
+ VDD
-
-ID/100
R 01
shunt
Fig.16. Avalanche energy test circuit.
WDSS = 0.5 ⋅ LID2 ⋅ BVDSS/(BVDSS − VDD)
April 1998 5 Rev 1.100
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet BUK9575-100A.PDF ] | |
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