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PDF BUK9640-100A Data sheet ( Hoja de datos )
| Número de pieza | BUK9640-100A | |
| Descripción | TrenchMOS transistor Logic level FET | |
| Fabricantes | NXP Semiconductors | |
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Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
BUK9540-100A
BUK9640-100A
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope available in
TO220AB and SOT404 . Using
’trench’ technology which features
very low on-state resistance. It is
intended for use in automotive and
general purpose switching
applications.
PINNING
TO220AB & SOT404
PIN DESCRIPTION
1 gate
2 drain
3 source
tab/mb drain
QUICK REFERENCE DATA
SYMBOL PARAMETER
VDS
ID
Ptot
Tj
RDS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
VGS = 5 V
VGS = 10 V
MAX.
100
37
138
175
40
39
PIN CONFIGURATION
mb tab
SYMBOL
d
2
13
SOT404
1 23
TO220AB
g
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDS
VDGR
±VGS
±VGSM
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Non-repetitive gate-source voltage
-
RGS = 20 kΩ
-
tp≤50µS
ID
ID
IDM
Ptot
Tstg, Tj
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
-
THERMAL RESISTANCES
SYMBOL
Rth j-mb
Rth j-a
Rth j-a
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient(TO220AB)
Thermal resistance junction to
ambient(SOT404)
CONDITIONS
-
in free air
Minimum footprint, FR4
board
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
100
100
10
15
37
26
149
138
175
TYP.
-
60
50
MAX.
1.1
-
-
UNIT
V
A
W
˚C
mΩ
mΩ
UNIT
V
V
V
V
A
A
A
W
˚C
UNIT
K/W
K/W
K/W
December 1999
1
Rev 1.000
1 page  
Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
BUK9540-100A
BUK9640-100A
VGS(TO) / V
2.5
max.
2
typ.
1.5
min.
1
0.5
0
-100
-50
0 50
Tj / C
100 150 200
Fig.11. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
1E-01
Sub-Threshold Conduction
1E-02
1E-03
2% typ 98%
1E-04
1E-05
1E-05
0 0.5 1 1.5 2 2.5
Fig.12. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
3
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0.01
0.1 1 10
VDS/V
Ciss
Coss
Crss
100
Fig.13. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
5
VGS / V
4
3
VDS = 14V
VDS = 44V
2
1
0
0 10 20 QG / nC 30 40 50
Fig.14. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 25 A; parameter VDS
Source-Drain Diode Current, IF (A)
50
VGS = 0 V
45
40
35
30 175 C
25
20 Tj = 25 C
15
10
5
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5
Source-Drain Voltage, VSDS (V)
Fig.15. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
WDSS%
120
110
100
90
80
70
60
50
40
30
20
10
0
20 40 60 80 100 120 140 160 180
Tmb / C
Fig.16. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 75 A
December 1999
5
Rev 1.000
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet BUK9640-100A.PDF ] | |
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