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부품번호 | BUK9675-55 기능 |
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기능 | TrenchMOS transistor Logic level FET | ||
제조업체 | NXP Semiconductors | ||
로고 | |||
전체 8 페이지수
Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
BUK9675-55
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope suitable for surface
mounting. Using ’trench’ technology
the device features very low on-state
resistance and has integral zener
diodes giving ESD protection up to
2kV. It is intended for use in
automotive and general purpose
switching applications.
QUICK REFERENCE DATA
SYMBOL PARAMETER
VDS
ID
Ptot
Tj
RDS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
VGS = 5 V
MAX.
55
19.7
61
175
75
PINNING - SOT404
PIN DESCRIPTION
1 gate
2 drain
3 source
mb drain
PIN CONFIGURATION
mb
2
13
SYMBOL
d
g
s
UNIT
V
A
W
˚C
mΩ
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDS
VDGR
±VGS
ID
ID
IDM
Ptot
Tstg, Tj
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
-
RGS = 20 kΩ
-
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
-
ESD LIMITING VALUE
SYMBOL
VC
PARAMETER
Electrostatic discharge capacitor
voltage, all pins
CONDITIONS
Human body model
(100 pF, 1.5 kΩ)
THERMAL RESISTANCES
SYMBOL
Rth j-mb
Rth j-a
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
-
Minimum footprint, FR4
board
MIN.
-
-
-
-
-
-
-
- 55
MAX.
55
55
10
19.7
13.9
79
61
175
UNIT
V
V
V
A
A
A
W
˚C
MIN.
-
MAX.
2
UNIT
kV
TYP.
-
50
MAX.
2.46
-
UNIT
K/W
K/W
April 1998 1 Rev 1.100
Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
BUK9675-55
50
ID/A
10.0 8.0 VGS/V =
6.0
40 5.4
5.0
4.8
4.6
30 4.4
4.2
4.0
20
3.8
3.6
3.4
3.2
10 3.0
2.8
2.6
2.4
0
0
2
4 VDS/V 6
2.2
8 10 2.0
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
90 RDS(ON)/mOhm
VGS/V =
85
80
75
4 4.2
4.4
4.6 5
4.8
70
65
60
55
5
Fig.6.
10 15 ID/A 20 25
Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
25
ID/A
20
15
10
5
Tj/C =
175
25
0
012345
VGS/V
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
Transconductance, gfs (S)
15
14
13
12
11
10
9
8
7
6
5 0 5 10 15 20 25
Drain current, ID (A)
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
2.5 a
BUK959-60 Rds(on) normlised to 25degC
2
1.5
1
0.5
-100
-50
0 50 100 150 200
Tmb / degC
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 10 A; VGS = 5 V
VGS(TO) / V
2.5
max.
2
typ.
1.5
min.
1
BUK959-60
0.5
0
-100
-50
0 50
Tj / C
100 150 200
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
April 1998 4 Rev 1.100
4페이지 Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
MECHANICAL DATA
Dimensions in mm
Net Mass: 1.4 g
10.3 max
4.5 max
1.4 max
11 max
15.4
Product specification
BUK9675-55
2.5
0.85 max
(x2)
0.5
2.54 (x2)
Fig.18. SOT404 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
11.5
9.0
17.5
2.0
3.8
5.08
Fig.19. SOT404 : soldering pattern for surface mounting.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Epoxy meets UL94 V0 at 1/8".
April 1998 7 Rev 1.100
7페이지 | |||
구 성 | 총 8 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
BUK9675-55 | TrenchMOS transistor Logic level FET | NXP Semiconductors |
BUK9675-55 | TrenchMOS transistor Logic level FET | NXP Semiconductors |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |