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Número de pieza | BUK9840-55 | |
Descripción | TrenchMOS transistor Logic level FET | |
Fabricantes | NXP Semiconductors | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de BUK9840-55 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
No Preview Available ! Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
BUK9840-55
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope suitable for surface
mounting. The device features very
low on-state resistance and has
integral zener diodes giving ESD
protection. It is intended for use in
automotive and general purpose
switching applications.
QUICK REFERENCE DATA
SYMBOL PARAMETER
VDS
ID
Ptot
Tj
RDS(ON)
Drain-source voltage
Drain current
Total power dissipation
Junction temperature
Drain-source on-state
resistance
VGS = 5 V
MAX.
55
10.7
1.8
150
40
PINNING - SOT223
PIN DESCRIPTION
1 gate
2 drain
3 source
4 drain (tab)
PIN CONFIGURATION
4
123
SYMBOL
d
g
s
UNIT
V
A
W
˚C
mΩ
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDS
VDGR
±VGS
ID
ID
ID
IDM
Ptot
Ptot
Tstg, Tj
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Total power dissipation
Storage & operating temperature
-
RGS = 20 kΩ
-
Tsp = 25 ˚C
On PCB in Fig.19
Tamb = 25 ˚C
On PCB in Fig.19
Tamb = 100 ˚C
Tsp = 25 ˚C
Tsp = 25 ˚C
On PCB in Fig.19
Tamb = 25 ˚C
-
ESD LIMITING VALUE
SYMBOL
VC
PARAMETER
Electrostatic discharge capacitor
voltage
CONDITIONS
Human body model
(100 pF, 1.5 kΩ)
MIN.
-
-
-
-
-
-
-
-
-
- 55
MAX.
55
55
10
10.7
5
3.1
40
8.3
1.8
150
UNIT
V
V
V
A
A
A
A
W
W
˚C
MIN.
-
MAX.
2
UNIT
kV
January 1998
1
Rev 1.000
1 page Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
BUK9840-55
1E-01
Sub-Threshold Conduction
1E-02
1E-03
2% typ 98%
1E-04
1E-05
1E-05
0 0.5 1 1.5 2 2.5
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
3
2.5
2.0
1.5
1.0 Ciss
0.5
0
0.01 0.1
1 VDS/V 10
Coss
Crss
100
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
6
VGS/V
5
4
VDS = 14V
3
VDS = 44V
2
1
0
0
5
10 QG/nC 15
20
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 9 A; parameter VDS
20
IF/A
15
10
Tj/C = 150
25
5
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4
VSDS/V
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
WDSS%
120
110
100
90
80
70
60
50
40
30
20
10
0
20 40 60 80 100 120 140
Tmb / C
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tsp); conditions: ID = 3.6 A
VGS
0
RGS
L
VDS
T.U.T.
+ VDD
-
-ID/100
R 01
shunt
Fig.16. Avalanche energy test circuit.
WDSS = 0.5 ⋅ LID2 ⋅ BVDSS/(BVDSS − VDD)
January 1998
5
Rev 1.000
5 Page |
Páginas | Total 9 Páginas | |
PDF Descargar | [ Datasheet BUK9840-55.PDF ] |
Número de pieza | Descripción | Fabricantes |
BUK9840-55 | TrenchMOS transistor Logic level FET | NXP Semiconductors |
BUK9840-55 | TrenchMOS transistor Logic level FET | NXP Semiconductors |
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