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PDF BS62LV256SI Data sheet ( Hoja de datos )

Número de pieza BS62LV256SI
Descripción Very Low Power/Voltage CMOS SRAM 32K X 8 bit
Fabricantes Brilliance Semiconductor 
Logotipo Brilliance Semiconductor Logotipo



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No Preview Available ! BS62LV256SI Hoja de datos, Descripción, Manual

BSI Very Low Power/Voltage CMOS SRAM
32K X 8 bit
BS62LV256
„ FEATURES
• Wide Vcc operation voltage : 2.4V ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade : 20mA (Max.) operating current
I- grade : 25mA (Max.) operating current
0.01uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade : 35mA (Max.) operating current
I- grade : 40mA (Max.) operating current
0.4uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns (Max.) at Vcc=3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
„ PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
BS62LV256SC
BS62LV256TC
BS62LV256PC
BS62LV256JC
BS62LV256DC
BS62LV256SI
BS62LV256TI
BS62LV256PI
BS62LV256JI
BS62LV256DI
0 O C to +70 O C
-40 O C to +85 O C
„ PIN CONFIGURATIONS
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1 28
2 27
3 26
4 25
5
6
BBSS6622LLVV225566SSIC2243
7 BS62LV256PC22
8 BS62LV256PI 21
9
BS62LV256JC
BS62LV256JI
20
10 19
11 18
12 17
13 16
14 15
VCC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
2.4V ~ 5.5V
2.4V ~ 5.5V
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
BS62LV256TC
BS62LV256TI
28 A10
27 CE
26 DQ7
25 DQ6
24 DQ5
23 DQ4
22 DQ3
21 GND
20 DQ2
19 DQ1
18 DQ0
17 A0
16 A1
15 A2
„ DESCRIPTION
The BS62LV256 is a high performance, very low power CMOS
Static Random Access Memory organized as 32,768 words by 8 bits
and operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.01uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by active LOW chip
enable (CE), active LOW output enable (OE) and three-state
output drivers.
The BS62LV256 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV256 is available in the DICE form, JEDEC standard
28pin 330mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP and
8mmx13.4mm TSOP (normal type).
SPEED
(ns)
Vcc=
3.0V
70
POWER DISSIPATION
STANDBY
Operating
(ICCSB1, Max)
(ICC, Max)
Vcc=
5.0V
Vcc=
3.0V
Vcc=
5.0V
Vcc=
3.0V
1uA 0.2uA 35mA 20mA
70 2uA 0.4uA 40mA 25mA
„ BLOCK DIAGRAM
PKG
TYPE
SOP-28
TSOP-28
PDIP-28
SOJ-28
DICE
SOP-28
TSOP-28
PDIP-28
SOJ-28
DICE
A5
A6
A7
A12
A14
A13
A8
A9
A11
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE
WE
OE
Vdd
Gnd
Address
Input
Buffer
18
Row
Decoder
512
Memory Array
512 x 512
8
8
Control
Data
Input
Buffer
Data
Output
Buffer
512
8 Column I/O
Write Driver
Sense Amp
8
64
Column Decoder
12
Address Input Buffer
A4 A3 A2 A1 A0 A10
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS62LV256
1
Revision 2.2
April 2001

1 page




BS62LV256SI pdf
BSI
„ SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
ADDRESS
D OUT
READ CYCLE2 (1,3,4)
t OH
t AA
t RC
CE
D OUT
READ CYCLE3 (1,4)
ADDRESS
OE
CE
D OUT
t ACS
t (5)
CLZ
t RC
t AA
t OE
t OLZ
t ACS
t (5)
CLZ
BS62LV256
t OH
t (5)
CHZ
t OH
t (5)
OHZ
t (1,5)
CHZ
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL .
5. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
R0201-BS62LV256
5
Revision 2.2
April 2001

5 Page





BS62LV256SI arduino
BSI
REVISION HISTORY
Revision Description
2.2 2001 Data Sheet release
BS62LV256
Date
Note
Apr. 15, 2001
R0201-BS62LV256
11
Revision 2.2
April 2001

11 Page







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