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BR24C04F-W 데이터시트 PDF




ROHM Semiconductor에서 제조한 전자 부품 BR24C04F-W은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 BR24C04F-W 자료 제공

부품번호 BR24C04F-W 기능
기능 I2C BUS compatible serial EEPROM
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BR24C04F-W 데이터시트, 핀배열, 회로
Memory ICs
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
I2C BUS compatible serial EEPROM
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W /
BR24C01AFV-W / BR24C02-W / BR24C02F-W /
BR24C02FJ-W / BR24C02FV-W / BR24C04-W /
BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
The BR24C01A-W, BR24C02-W, and BR24C04-W series are 2-wire (I2C BUS type) serial EEPROMs which are
electrically programmable.
I2C BUS is a registered trademark of Philips.
!Applications
VCRs, TVs, printers, car stereos, cordless telephones, short wave radios, programmable DIP switches
!Features
1) 128×8bits (1k) serial EEPROM.
(BR24C01A-W / AF-W / AFJ-W / AFV-W)
256×8bits (2k) serial EEPROM.
(BR24C02-W / F-W / FJ-W / FV-W)
512×8bits (4k) serial EEPROM.
(BR24C04-W / F-W / FJ-W / FV-W)
2) Two wire serial interface.
3) Operating voltage range : 2.7V5.5V
4) Low current consumption
Active (at 5V) : 1.5mA (Typ.)
Standby (at 5V) : 0.1µA (Typ.)
5) Auto erase and auto complete functions can be used
during write operations.
6) Page write function.
BR24C01A-W / AF-W / AFJ-W / AFV-W : 8 bytes
BR24C02-W / F-W / FJ-W / FV-W : 8 bytes
BR24C04-W / F-W / FJ-W / FV-W : 16 bytes
7) DATA security
Write protect feature
Inhibit to WRITE at low VCC
8) Noise filters at SCL and SDA pins.
9) Address can be incremented automatically during
read operations.
10) Compact packages.
11) Rewriting possible up to 100,000 times
12) Data can be stored for ten years without corruption.
!Absolute maximum ratings (Ta = 25°C)
Parameter
Symbol
Limits
Applied voltage
Power dissipation
VCC 0.3~+6.5
300(SSOPB8)
1
Pd 450(SOP8, SOPJ8) 2
800(DIP8)
3
Storage temperature
Tstg
65~+125
Operating temperature
Topr
40~+85
Input voltage
− −0.3~VCC+0.3
1 Reduced by 3.0mW for each increase in Ta of 1°C over 25°C.
2 Reduced by 4.5mW for each increase in Ta of 1°C over 25°C.
3 Reduced by 8.0mW for each increase in Ta of 1°C over 25°C.
Unit
V
mW
°C
°C
V




BR24C04F-W pdf, 반도체, 판매, 대치품
Memory ICs
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
!Timing charts
SCL
SDA
(input)
SDA
(output)
tHD : STA
tBUF
tR tF tHIGH
tSU : DAT
tLOW
tHD : DAT
tPD tDH
SCL
SDA
tSU : STA
tHD : STA
tSU : STO
START BIT
STOP BIT
· Data is read on the rising edge of SCL.
· Data is output in synchronization with the falling edge of SCL.
Fig.1 Synchronized data input / output timing
SCL
SDA
D0
Write data
(n address)
ACK
Stop condition
tWR
Start condition
Fig.2 Write cycle timing
!Circuit operation
(1) Start condition (recognition of start bit)
Before executing any command, when SCL is HIGH, a start condition (start bit) is required to cause SDA to fall from
HIGH to LOW. This IC is designed to constantly detect whether there is a start condition (start bit) for the SDA and
SCL line, and no commands will be executed unless this condition is satisfied.
(See Fig.1 for the synchronized data input / output timing.)
(2) Stop condition (recognition of stop bit)
To stop any command, a stop condition (stop bit) is required. A stop condition is achieved when SDA goes from
LOW to HIGH while SCL is HIGH. This enables commands to be completed.
(See Fig.1 for the synchronized data input / output timing.)
(3) Precautions concerning write commands
In the WRITE mode, the transferred data is not written to the memory unless the stop bit is executed.

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BR24C04F-W 전자부품, 판매, 대치품
Memory ICs
BR24C01A-W / BR24C01AF-W / BR24C01AFJ-W / BR24C01AFV-W / BR24C02-W / BR24C02F-W /
BR24C02FJ-W / BR24C02FV-W / BR24C04-W / BR24C04F-W / BR24C04FJ-W / BR24C04FV-W
BR24C02-W / F-W / FJ-W / FV-W
S
T
A
R SLAVE
T ADDRESS
W
R
I
T
E
SDA
LINE
1 0 1 0 A2 A1 A0
WA
7
WORD
ADDRESS
WA
0
D7
DATA
S
T
O
P
D0
RA A A
/C C C
WK K K
WP
Fig.5
BR24C04-W / F-W / FJ-W / FV-W
SW
TR
AI
R SLAVE T
T ADDRESS E
SDA
LINE
1 0 1 0 A2 A1 PS
WA
7
WORD
ADDRESS
WA
0
D7
RA
/C
WK
A
C
K
WP
DATA
S
T
O
P
D0
A
C
K
Fig.6
Data is written to the address designated by the word address (n address).
After eight bits of data are input, the data is written to the memory cell by issuing the stop bit.
(8) Page write cycle
BR24C01A-W / AF-W / AFJ-W / AFV-W
SW
TR
AI
R
SLAVE
T
T ADDRESS E
WORD
ADDRESS(n)
DATA(n)
SDA
LINE
1 0 1 0 A2 A1 A0
WA
6
WA
0
D7
D0
DATA(n+7)
S
T
O
P
D0
RA
/C
WK
AA
CC
KK
A
C
K
WP
Fig.7

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부품번호상세설명 및 기능제조사
BR24C04F-W

I2C BUS compatible serial EEPROM

ROHM Semiconductor
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