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BR24E16 데이터시트 PDF




ROHM Semiconductor에서 제조한 전자 부품 BR24E16은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 BR24E16 자료 제공

부품번호 BR24E16 기능
기능 I2C BUS compatible serial EEPROM
제조업체 ROHM Semiconductor
로고 ROHM Semiconductor 로고


BR24E16 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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BR24E16 데이터시트, 핀배열, 회로
Memory Ics
BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F /
BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV
I2C BUS compatible serial EEPROM
BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV /
BR24C16 / BR24C16F / BR24C16FJ / BR24C16FV /
BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV /
The BR24C08, BR24C16 and BR24E16 series are 2-wire (I2C BUS type) serial EEPROMs which are electrically
programmable.
I2C BUS is a registered trademark of Philips.
zFeatures
1) 1k x 8 bits serial EEPROM.
(BR24C08 / F / FJ / FV)
2k x 8 bits serial EEPROM.
(BR24C16 / F / FJ / FV, BR24E16 / F / FJ / FV)
2) Two wire serial interface.
(2Byte Address : BR24E16)
3) Operating voltage range : 2.7V5.5V
4) Low current consumption
Active (at 5V) : 2.0mA (Typ.)
Standby (at 5V) : 1.0µA (Typ.)
5) Auto erase and auto complete functions can be used
during write operations.
6) Page write function : 16byte
7) DATA security
Write protect feature
Inhibit to WRITE at low Vcc
8) Noise filters at SCL and SDA pins.
9) Address can be incremented automatically during
read operations.
10) Compact packages.
11) Rewriting possible up to 100,000 times.
12) Data can be stored for ten years without corruption.
zAbsolute maximum ratings (Ta=25°C)
Parameter
Symbol
Limits
Supply voltage
VCC 0.3~+6.5
300(SSOPB8)
1
Power dissipation
Pd 450(SOP8, SOPJ8) 2
800(DIP8)
3
Storage temperature range
Tstg
65~+125
Operating temperature range
Topr
40~+85
Terminal voltage
− −0.3~VCC+0.3
1 Reduced by 3.0mW for each increase in Ta of 1°C over 25°C.
2 Reduced by 3.5mW for each increase in Ta of 1°C over 25°C.
3 Reduced by 5.0mW for each increase in Ta of 1°C over 25°C.
Unit
V
mW
°C
°C
V
zRecommended operating conditions (Ta=25°C)
Parameter
Symbol
Limits
Power supply voltage
Input voltage
VCC
VIN
2.7~5.5
0~VCC
Unit
V
V




BR24E16 pdf, 반도체, 판매, 대치품
Memory Ics
BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F /
BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV
zTiming charts
SCL
SDA
(IN)
SDA
(OUT)
tHD : STA
tBUF
tR tF tHIGH
tSU : DAT
tLOW
tHD : DAT
tPD tDH
SCL
SDA
tSU : STA
tHD : STA
tSU : STO
START BIT
STOP BIT
Data is read on the rising edge of SCL.
Data is output in synchronization with the falling edge of SCL.
Fig.1 Synchronized data input / output timing
SCL
SDA
D0
Write data (n)
ACK
tWR
STOP CONDITION
START CONDITION
Fig.2 Write cycle timing
zCircuit operation
(1) Start condition (recognition of start bit)
Before executing any command, when SCL is HIGH, a start condition (start bit) is required to cause SDA to fall from
HIGH to LOW. This IC is designed to constantly detect whether there is a start condition (start bit) for the SDA and
SCL line, and no commands will be executed unless this condition is satisfied.
(See Fig.1 for the synchronized data input / output timing.)
(2) Stop condition (recognition of stop bit)
To stop any command, a stop condition (stop bit) is required. A stop condition is achieved when SDA goes from LOW
to HIGH while SCL is HIGH. This enables commands to be completed.
(See Fig.1 for the synchronized data input / output timing.)
(3) Precautions concerning write commands
In the WRITE mode, the transferred data is not written to the memory unless the stop bit is executed.

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BR24E16 전자부품, 판매, 대치품
Memory Ics
BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F /
BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV
(7) Byte write
BR24C08 / F / FJ / FV
S
T
A
R SLAVE
T ADDRESS
W
R
I
T
E
SDA
LINE
1 0 1 0 A2 P1 P0
WA
7
WORD
ADDRESS
WA
0
D7
RA
/C
WK
A
C
K
WP
DATA
S
T
O
P
D0
A
C
K
Fig.4
BR24C16 / F / FJ / FV
S
T
A
R SLAVE
T ADDRESS
W
R
I
T
E
SDA
LINE
1 0 1 0 P2 P1 P0
WA
7
WORD
ADDRESS
WA
0
D7
RA
/C
WK
A
C
K
WP
DATA
S
T
O
P
D0
A
C
K
Fig.5
BR24E16 / F / FJ / FV
S
T
A
R SLAVE
T ADDRESS
W
R
I
T
E
1st WORD
ADDRESS
SDA
LINE
1 0 1 0 A2 A1 A0
WA
10
2nd WORD
ADDRESS
WA
0
D7
DATA
S
T
O
P
D0
RA
/C
WK
AA
CC
KK
A
C
K
WP
Fig.6
$ Data is written to the address designated by the word address (n address).
$ After 8 bits of data are input, the data is written to the memory cell by issuing the stop bit.

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